A fabrication guide for planar silicon quantum dot heterostructures

TL;DR

This paper provides a comprehensive fabrication guide for creating high-quality planar silicon quantum dots, emphasizing process considerations to optimize device performance and reproducibility.

Contribution

It offers detailed insights into fabrication processes and considerations for silicon quantum dots, addressing often overlooked aspects in the literature.

Findings

Optimized fabrication processes reduce defects and disorder.

Techniques enable creation of low-disorder silicon quantum dots.

Guidelines applicable to various low-dimensional systems.

Abstract

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.