Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

TL;DR

This paper evaluates the performance of the first 2D prototype of VIPRAM, demonstrating its suitability for high-speed pattern recognition in HL-LHC conditions and readiness for 3D integration.

Contribution

It presents the design and extensive performance testing of the protoVIPRAM00 chip, a key step towards 3D-IC based pattern recognition for HL-LHC triggers.

Findings

Operates at 100 MHz with perfect correctness in realistic conditions

Building blocks are ready for 3D stacking

Performance boundary characterized under extreme conditions

Abstract

Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The first step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.