On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory

TL;DR

This paper presents a hardware architecture for Hierarchical Temporal Memory (HTM) tailored for on-chip face recognition, leveraging memristive technology to improve speed and reduce memory usage, achieving higher accuracy with many training images.

Contribution

It introduces a novel memristive HTM architecture with a learning mechanism for face recognition, optimizing memory and processing efficiency compared to prior software-based approaches.

Findings

Achieves 83.5% accuracy with large training sets.

Reduces memory requirements by consolidating templates.

Increases processing speed through hardware design.

Abstract

Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5\%) compared to only Spatial Pooler design presented in the previous works.