VLSI Designs for Joint Channel Estimation and Data Detection in Large SIMO Wireless Systems

TL;DR

This paper introduces a novel joint channel estimation and data detection algorithm called PrOX for large SIMO wireless systems, offering improved performance and efficiency through specialized VLSI architectures.

Contribution

It proposes the PrOX algorithm based on biconvex relaxation for efficient joint estimation and detection, along with scalable VLSI designs for high-throughput implementation.

Findings

PrOX outperforms existing JED designs in throughput.

PrOX achieves higher hardware and energy efficiency.

Theoretical convergence of PrOX is established.

Abstract

Channel estimation errors have a critical impact on the reliability of wireless communication systems. While virtually all existing wireless receivers separate channel estimation from data detection, it is well known that joint channel estimation and data detection (JED) significantly outperforms conventional methods at the cost of high computational complexity. In this paper, we propose a novel JED algorithm and corresponding VLSI designs for large single-input multiple-output (SIMO) wireless systems that use constant-modulus constellations. The proposed algorithm is referred to as PRojection Onto conveX hull (PrOX) and relies on biconvex relaxation (BCR), which enables us to efficiently compute an approximate solution of the maximum-likelihood JED problem. Since BCR solves a biconvex problem via alternating optimization, we provide a theoretical convergence analysis for PrOX. We design a scalable, high-throughput VLSI architecture that uses a linear array of processing elements to minimize hardware complexity. We develop corresponding field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs, and we demonstrate that PrOX significantly outperforms the only other existing JED design in terms of throughput, hardware-efficiency, and energy-efficiency.