Energy-Efficient Wireless Interconnection Framework for Multichip Systems with In-package Memory Stacks

TL;DR

This paper proposes an energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks, aiming to reduce energy and latency while increasing bandwidth compared to traditional wired solutions.

Contribution

It introduces a novel wireless interconnection network design for multichip systems, demonstrating significant improvements over existing wired inter-chip communication methods.

Findings

Reduces energy consumption compared to wired channels.

Lowers latency in multichip communication.

Increases data bandwidth in multichip systems.

Abstract

Multichip systems with memory stacks and various processing chips are at the heart of platform based designs such as servers and embedded systems. Full utilization of the benefits of these integrated multichip systems need a seamless, and scalable in-package interconnection framework. However, state-of-the-art inter-chip communication requires long wireline channels which increases energy consumption and latency while decreasing data bandwidth. Here, we propose the design of an energy-efficient, seamless wireless interconnection network for multichip systems. We demonstrate with cycle-accurate simulations that such a design reduces the energy consumption and latency while increasing the bandwidth in comparison to modern multichip integration systems.