Sensitivity Challenge of Steep Transistors

TL;DR

This paper investigates the sensitivity issues of steep transistors like TFETs and NC-FETs, revealing high sensitivity to design parameters and proposing a novel dielectric-engineered TFET to address leakage problems.

Contribution

The study provides a detailed analysis of the sensitivity challenges in steep transistors and introduces a new DE-TFET design to mitigate leakage issues.

Findings

Conventional TFETs and NC-FETs exhibit high sensitivity to device parameters.

DE-TFETs based on 2D materials have reduced sensitivity but face leakage issues.

A novel DE-TFET design is proposed to overcome leakage while maintaining low sensitivity.

Abstract

Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of these devices in integrated circuits. From a sensitivity perspective, an ideal switch should have a high sensitivity to the gate voltage and lower sensitivity to the device design parameters like oxide and body thicknesses. In this work, conventional tunnel-FET (TFET) and negative capacitance FET are shown to suffer from high sensitivity to device design parameters using full-band atomistic quantum transport simulations and analytical analysis. Although Dielectric Engineered (DE-) TFETs based on 2D materials show smaller sensitivity compared with the conventional TFETs, they have leakage issue. To mitigate this challenge, a novel DE-TFET design has been proposed and studied.