Multi-level Memristive Memory with Resistive Networks

TL;DR

This paper introduces a novel multi-level memristive memory design using resistive networks, enabling scalable analog data storage with improved output levels and practical implementation considerations.

Contribution

The paper presents a new discrete state memory cell design combining memristors and resistive networks, enhancing multi-level storage capabilities over previous memristor-based memories.

Findings

Achieved 10 and 27 output levels in the memory cell.

Demonstrated increased output levels compared to prior memristor memory designs.

Analyzed issues related to level distinction and signal oscillations.

Abstract

Analog memory is of great importance in neurocomputing technologies field, but still remains difficult to implement. With emergence of memristors in VLSI technologies the idea of designing scalable analog data storage elements finds its second wind. A memristor, known for its history dependent resistance levels, independently can provide blocks of binary or discrete state data storage. However, using single memristor to save the analog value is practically limited due to the device variability and implementation complexity. In this paper, we present a new design of discrete state memory cell consisting of subcells constructed from a memristor and its resistive network. A memristor in the sub-cells provides the storage element, while its resistive network is used for programming its resistance. Several sub-cells are then connected in parallel, resembling potential divider configuration. The output of the memory cell is the voltage resulting from distributing the input voltage among the sub-cells. Here, proposed design was programmed to obtain 10 and 27 different output levels depending on the configuration of the combined resistive networks within the sub-cell. Despite the simplicity of the circuit, this realization of multilevel memory provides increased number of output levels compared to previous designs of memory technologies based on memristors. Simulation results of proposed memory are analyzed providing explicit data on the issues of distinguishing discrete analog output levels and sensitivity of the cell to oscillations in write signal patterns.