High Coherence Plane Breaking Packaging for Superconducting Qubits

TL;DR

This paper introduces a pogo pin packaging method for superconducting qubits with complex layouts, demonstrating comparable performance to traditional packages and low crosstalk, enabling more flexible quantum processor designs.

Contribution

The paper presents a novel pogo pin packaging approach for superconducting qubits with complex layouts, showing low crosstalk and comparable performance to standard packages.

Findings

Pogo pin packages perform comparably to wirebonded packages at 10 mK.

Crosstalk levels are below -40 dB at qubit frequencies.

The packaging method supports complex qubit layouts with modest manufacturing tolerances.

Abstract

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking. More detailed crosstalk measurements indicate levels of crosstalk less than -40 dB at the qubit frequencies, opening the possibility of integration with extensible qubit architectures.