Cost Modeling and Projection for Stacked Nanowire Fabric

TL;DR

This paper presents a cost analysis of the SN3D stacked nanowire 3-D integration approach, demonstrating significant reductions in area, interconnects, and overall cost compared to 2-D CMOS and other 3-D technologies.

Contribution

It introduces a detailed cost model for SN3D, comparing its scalability and cost advantages over existing 2-D and 3-D IC technologies.

Findings

SN3D reduces die area by up to 86%.

SN3D decreases interconnect length and distribution significantly.

SN3D achieves around 70% cost reduction compared to other technologies.

Abstract

To continue scaling beyond 2-D CMOS with 3-D integration, any new 3-D IC technology has to be comparable or better than 2-D CMOS in terms of scalability, enhanced functionality, density, power, performance, cost, and reliability. Transistor-level 3-D integration carries the most potential in this regard. Recently, we proposed a stacked horizontal nanowire based transistor-level 3-D integration approach, called SN3D [1][2] that solves scaling challenges and achieves tremendous benefits with respect to 2-D CMOS while keeping manageable thermal profile. In this paper, we present the cost analysis of SN3D and show comparison with 2-D CMOS (2D), conventional TSV based 3-D (T3D) and Monolithic 3-D integrations (M3D). In our cost model, we capture the implications of manufacturing, circuit density, interconnects, bonding and heat in determining die cost, and evaluate how cost scales as transistor count increases. Since SN3D is a new 3-D IC fabric, based on our proposed manufacturing pathway[1] we assumed complexity of fabrication steps as proportionality constants in our cost estimation model. Our analysis revealed 86%, 72% and 74% reduction in area; 55%, 43% and 43% reduction in interconnects distribution and total interconnect length for SN3D, which largely contributed to 70%, 67% and 68% reduction in cost in comparison to 2D, T3D and M3D respectively.