Progress-Space Tradeoffs in Single-Writer Memory Implementations

TL;DR

This paper introduces a space-efficient simulation of single-writer memory in distributed systems, adapting the number of multi-writer multi-reader registers to different progress conditions, and proves optimality for certain cases.

Contribution

It presents a novel algorithm that uses n+k-1 registers for k-lock-free SWMR memory simulation and establishes a matching lower bound, demonstrating space optimality.

Findings

Algorithm uses n+k-1 registers for k-lock-freedom.

Lower bound of n+1 registers for 2-lock-freedom matches the algorithm's space.

Supports conjecture that space complexity for k-obstruction-free and k-lock-free is similar.

Abstract

Most algorithms designed for shared-memory distributed systems assume the single-writer multi-reader (SWMR) setting where each process is provided with a unique register readable by all. In a system where computation is performed by a bounded number n of processes coming from a very large (possibly unbounded) set of potential participants, the assumption of a SWMR memory is no longer reasonable. If only a bounded number of multi-writer multi-reader (MWMR) registers are provided, we cannot rely on an a priori assignment of processes to registers. In this setting, simulating SWMR memory, or equivalently, ensuring stable writing (i.e., every written value persists in the memory), is desirable. In this paper, we propose a SWMR simulation that adapts the number of MWMR registers used to the desired progress condition. For any given k from 1 to n, we present an algorithm that uses only n+k-1 registers to simulate a k-lock-free SWMR memory. We also give a matching lower bound of n+1 registers required for the case of 2-lock-freedom, which supports our conjectures that the algorithm is space-optimal. Our lower bound holds for the strictly weaker progress condition of 2-obstruction-freedom, which suggests that the space complexity for k-obstruction-free and k-lock-free SWMR simulations might coincide.