Design of Adiabatic MTJ-CMOS Hybrid Circuits

TL;DR

This paper presents a novel adiabatic hybrid MTJ-CMOS circuit design that significantly reduces power consumption for logic-in-memory applications, demonstrating over seven times lower power use than non-adiabatic counterparts.

Contribution

It introduces a new adiabatic hybrid MTJ/CMOS structure for logic circuits, optimized for low power consumption in portable devices.

Findings

Over 7 times lower power consumption compared to non-adiabatic designs

Successful simulation of logic gates and full adder using 32nm CMOS technology

Potential for extending low-power logic-in-memory architectures

Abstract

Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic-in-memory structures in conjunction with CMOS. In this paper, we introduce a novel adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits. The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower power consumtion compared to the previous MTJ/CMOS full adder.