D3NOC: Dynamic Data-Driven Network On Chip in Photonic Electronic Hybrids

TL;DR

This paper introduces a reconfigurable hybrid photonic-electronic Network-on-Chip that dynamically adapts based on environmental feedback, significantly reducing latency and power consumption while increasing throughput.

Contribution

It presents a novel DDDAS-based hybrid photonic-plasmonic NoC with dynamic reconfiguration capabilities and demonstrates substantial performance and power efficiency improvements.

Findings

Up to 89% latency reduction

Up to 67% dynamic power savings

Enhanced throughput in reconfigurable NoC

Abstract

In this paper, we present a reconfigurable hybrid Photonic-Plasmonic Network-on-Chip (NoC) based on the Dynamic Data Driven Application System (DDDAS) paradigm. In DDDAS computations and measurements form a dynamic closed feedback loop in which they tune one another in response to changes in the environment. Our proposed system enables dynamic augmentation of a base electrical mesh topology with an optical express bus during the run-time. In addition, the measurement process itself adjusts to the environment. In order to achieve lower latencies, lower dynamic power, and higher throughput, we take advantage of a Configurable Hybrid Photonic Plasmonic Interconnect (CHyPPI) for our reconfigurable connections. We evaluate the performance and power of our system against kernels from NAS Parallel Benchmark (NPB) in addition to some synthetically generated traffic. In comparison to a 16x16 base electrical mesh, D3NOC shows up to 89% latency and 67% dynamic power net improvements beyond overhead-corrected performance. It should be noted that the design-space of NoC reconfiguration is vast and the goal of this study is not design-space exploration. Our goal is to show the potentials of adaptive dynamic measurements when coupled with other reconfiguration techniques in the NoC context.