A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

TL;DR

This paper introduces a scalable multi-core neuromorphic architecture with heterogeneous memory and routing strategies, enabling efficient event traffic management and supporting diverse neural network models in real-time applications.

Contribution

It presents a novel routing methodology combining hierarchical and mesh strategies with heterogeneous memory, validated on a prototype chip for improved scalability and flexibility.

Findings

Reduced memory requirements and latency in neuromorphic systems

Successful real-time classification of visual symbols using DVS data

Enhanced programmability for various neural network architectures

Abstract

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.