Hysteresis in the transfer characteristics of MoS2 transistors

TL;DR

This paper explores the causes of hysteresis in MoS2 transistors, highlighting the roles of water, defects, and environmental factors, and suggests potential applications in memory devices.

Contribution

It identifies water-facilitated charge trapping and intrinsic defects as key factors in hysteresis, providing insights for improving MoS2 transistor stability and memory applications.

Findings

Hysteresis increases with gate voltage, pressure, temperature, and light.

Step-like hysteresis behavior occurs around room temperature due to water trapping.

Intrinsic defects like S vacancies contribute to charge trapping.

Abstract

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.