A Pattern Recognition Approach to Transistor Array Parameter Variance

TL;DR

This paper applies pattern recognition techniques like PCA and LDA to analyze parameter variance in bipolar junction transistors within arrays, revealing significant inter-array differences and effective clustering based on device characteristics.

Contribution

It introduces an experimental approach using PCA and LDA to quantify and visualize transistor parameter variations, highlighting differences between arrays and improving device classification.

Findings

Most variance captured by two PCA axes

LDA effectively clusters transistors by array

PCA-based harmonic distortion mapping improves separation

Abstract

The properties of bipolar junction transistors (BJTs) are known to vary in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters.