Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning

TL;DR

This paper introduces a netlist analysis and fault injection-based classification method for FPGA scrubbing, improving error detection and reducing repair time by up to 48.5%.

Contribution

It presents a novel circuit analysis technique and floorplanning strategy to optimize FPGA scrubbing and error recovery.

Findings

Reduced Mean-Time-To-Repair by up to 48.5%

Early error detection through optimized scrubbing

Effective classification of critical configuration bits

Abstract

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches.