A Wait-free Multi-word Atomic (1,N) Register for Large-scale Data Sharing on Multi-core Machines
Mauro Ianni, Alessandro Pellegrini, Francesco Quaglia

TL;DR
This paper introduces ARC, a wait-free multi-word atomic register for multi-core systems that supports over 4 billion concurrent readers, improves scalability, and maintains constant-time read/write operations, suitable for cloud environments.
Contribution
ARC is a novel wait-free multi-word register that significantly increases reader capacity and reduces memory copying, enhancing scalability and performance on multi-core machines.
Findings
Supports up to 2^{32}-2 readers on 64-bit systems
Achieves constant-time reads and amortized constant-time writes
Demonstrates resilience in virtualized cloud environments
Abstract
We present a multi-word atomic (1,N) register for multi-core machines exploiting Read-Modify-Write (RMW) instructions to coordinate the writer and the readers in a wait-free manner. Our proposal, called Anonymous Readers Counting (ARC), enables large-scale data sharing by admitting up to concurrent readers on off-the-shelf 64-bits machines, as opposed to the most advanced RMW-based approach which is limited to 58 readers. Further, ARC avoids multiple copies of the register content when accessing it---this affects classical register's algorithms based on atomic read/write operations on single words. Thus it allows for higher scalability with respect to the register size. Moreover, ARC explicitly reduces improves performance via a proper limitation of RMW instructions in case of read operations, and by supporting constant time for read operations and amortized constant time for…
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