Computing via material topology optimisation

TL;DR

This paper demonstrates how to implement logical gates and a binary half-adder using topology optimisation of conductive material layouts to control heat conduction paths.

Contribution

It introduces a novel approach to computing by designing material layouts that perform logical operations through heat conduction optimization.

Findings

Successfully implemented AND and XOR gates

Designed a one-bit binary half-adder

Showed logical functions can be realized via material topology optimization

Abstract

We construct logical gates via topology optimisation (aimed to solve a station problem of heat conduction) of a conductive material layout. Values of logical variables are represented high and low values of a temperature at given sites. Logical functions are implemented via the formation of an optimum layout of conductive material between the sites with loading conditions. We implement AND and XOR gates and a one-bit binary half-adder.