Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits

TL;DR

This paper develops mathematical formulas to estimate the logical masking capability of majority and minority gates in nanoelectronic circuits, comparing them with traditional gates and analyzing how fan-in affects their masking ability.

Contribution

It introduces novel mathematical formulae for evaluating the logical masking capability of majority/minority gates in nanoelectronic circuit synthesis.

Findings

Logical masking capability of majority/minority gates is similar to XOR/XNOR gates.

Logical masking capability increases with fan-in.

Formulas hold well for both majority and minority gates.

Abstract

In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used extensively in nanoelectronic digital circuit synthesis. The mathematical formulae derived to evaluate the logical masking capability of majority gates holds well for minority gates, and a comparison with the logical masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR is provided. It is inferred from this research work that the logical masking capability of majority/minority gates is similar to that of XOR/XNOR gates, and with an increase of fan-in the logical masking capability of majority/minority gates also increases.