Variable Instruction Fetch Rate to Reduce Control Dependent Penalties

TL;DR

This paper proposes two new instruction fetch micro-architectural methods to reduce penalties from hard-to-predict branches, demonstrating a 29.4% IPC improvement on benchmark simulations.

Contribution

Introduction of two novel instruction fetch techniques and evaluation of their performance against existing multi-branch fetch policies.

Findings

29.4% average IPC improvement on SPEC benchmarks

Effective in wide pipeline machine simulations

Potential applications in high-performance scientific computing

Abstract

In order to overcome the branch execution penalties of hard-to-predict instruction branches, two new instruction fetch micro-architectural methods are proposed in this paper. In addition, to compare performance of the two proposed methods, different instruction fetch policy schemes of existing multi-branch path architectures are evaluated. An improvement in Instructions Per Cycle (IPC) of 29.4% on average over single-thread execution with gshare branch predictor on SPEC 2000/2006 benchmark is shown. In this paper, wide pipeline machines are simulated for evaluation purposes. The methods discussed in this paper can be extended to High Performance Scientific Computing needs, if the demands of IPC improvement are far more critical than $cost.