Pipelined Parallel FFT Architecture

TL;DR

This paper introduces an optimized pipelined VLSI architecture for FFT that uses parallel processing to enhance speed and efficiency, reducing hardware complexity and operation time.

Contribution

It presents a novel pipelined Radix-2 FFT architecture with parallel processing, improving speed and hardware efficiency over traditional designs.

Findings

Enhanced processing speed due to pipelining and parallelism

Reduced hardware complexity and cost

Improved FFT computation efficiency

Abstract

In this paper, an optimized efficient VLSI architecture of a pipeline Fast Fourier transform (FFT) processor capable of producing the reverse output order sequence is presented. Paper presents Radix-2 multipath delay architecture for FFT calculation. The implementation of FFT in hardware is very critical because for calculation of FFT number of butterfly operations i.e. number of multipliers requires due to which hardware gets increased means indirectly cost of hardware is automatically gets increased. Also multiplier operations are slow that's why it limits the speed of operation of architecture. The optimized VLSI implementation of FFT algorithm is presented in this paper. Here architecture is pipelined to optimize it and to increase the speed of operation. Also to increase the speed of operation 2 levels parallel processing is used.