# One random jump and one permutation: sufficient conditions to chaotic, statistically faultless, and large throughput PRNG for FPGA

## TL;DR

This paper introduces a new chaos-based FPGA pseudorandom number generator using a Hamilton cycle deletion and permutation, achieving high throughput and passing rigorous statistical tests, with potential security and performance benefits.

## Contribution

The paper presents a novel chaos-based FPGA PRNG that combines Hamilton cycle deletion and permutation, achieving high speed and passing comprehensive statistical tests.

## Key findings

- Achieves a throughput of 6.7 Gbps.
- Successfully passes the TestU01 battery of tests.
- Outperforms most existing FPGA PRNGs in statistical quality.

## Abstract

Sub-categories of mathematical topology, like the mathematical theory of chaos, offer interesting applications devoted to information security. In this research work, we have introduced a new chaos-based pseudorandom number generator implemented in FPGA, which is mainly based on the deletion of a Hamilton cycle within the $n$-cube (or on the vectorial negation), plus one single permutation. By doing so, we produce a kind of post-treatment on hardware pseudorandom generators, but the obtained generator has usually a better statistical profile than its input, while running at a similar speed. We tested 6 combinations of Boolean functions and strategies that all achieve to pass the most stringent TestU01 battery of tests. This generation can reach a throughput/latency ratio equal to 6.7 Gbps, being thus the second fastest FPGA generator that can pass TestU01.