Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training

TL;DR

This paper proposes an analog CMOS-based resistive processing unit (RPU) design that can locally store and process data in parallel, aiming to accelerate deep neural network training beyond current software-based methods.

Contribution

Introduction of a novel analog CMOS RPU architecture capable of local data storage and parallel processing for efficient DNN training acceleration.

Findings

Analyzed the properties of the CMOS RPU for functionality.

Evaluated the feasibility of CMOS RPU for DNN training acceleration.

Demonstrated potential advantages over existing non-volatile memory-based RPUs.

Abstract

Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.