# A Thermodynamic Perspective of Negative-capacitance Field-effect-transistors

## TL;DR

This paper presents a unified simulation framework for ferroelectric FETs, combining thermodynamics and polarization dynamics to analyze hysteresis and negative capacitance effects for memory and logic applications.

## Contribution

It introduces a comprehensive simulation approach that integrates ferroelectric thermodynamics with semiconductor electrostatics and carrier transport.

## Key findings

- Demonstrates regimes of hysteresis switching and high on-current operation
- Shows negative capacitance effect can reduce subthreshold slope
- Identifies ferroelectric thickness as a key parameter

## Abstract

Physical phenomena underlying operation of ferroelectric field-effect transistors (FeFETs) is treated within a unified simulation framework. The framework incorporates the Landau mean-field treatment of free energy of a ferroelectric and the polarization dynamics according to Landau-Khalatnikov (LK) equation. These equations are self-consistently solved with the one-dimensional metal-oxide-semiconductor (MOS) structure electrostatics and the drift-diffusion solution for the current in the semiconductor channel. Numerical simulations demonstrate, depending on the ferroelectric (FE) thickness, both regimes of hysteresis switching (relevant for a non-volatile memory) and of higher on-currents and steeper subthreshold slope (SS) with a negligible hysteresis (relevant for logic) via the negative capacitance effect.