# Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

## TL;DR

This paper presents the design and characterization of a high-voltage CMOS sensor chip for the CLIC vertex detector, demonstrating promising performance metrics in standalone tests.

## Contribution

It introduces a capacitively coupled HV-CMOS sensor chip designed for CLIC, with detailed standalone characterization results.

## Key findings

- Rise time of ~20 ns
- Charge gain of 190 mV/ke^-
- Noise level of ~40 e^- RMS

## Abstract

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $\mu$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $\Omega$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $\mu$W/pixel. The main design aspects, as well as standalone measurement results, are presented.