# Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs

## TL;DR

This study uses device simulations to analyze how neutron strikes can cause multiple FinFET transistors to be affected, revealing the spatial extent and factors influencing charge collection in 14nm technology.

## Contribution

It provides the first detailed simulation-based characterization of neutron-induced charge collection effects in 14nm FinFETs, highlighting the impact on multiple transistors and the influence of device geometry.

## Key findings

- Multiple transistors can be affected up to 200nm from the strike point.
- Charge collection is influenced by the potential of source/drain regions.
- In multi-fin FinFETs, charge per fin decreases as the number of fins increases.

## Abstract

FinFETs have replaced the conventional bulk CMOS transistors in the sub-20nm technology. One of the key issues to consider is, the vulnerability of FinFET based circuits to multiple node charge collection due to neutron-induced strikes. In this paper, we perform a device simulation based characterization study on representative layouts of 14nm bulk FinFETs in order to study the extent to which multiple transistors are affected. We find that multiple transistors do get affected and the impact can last up to five transistors away (~200nm). We show that the potential of source/drain regions in the neighborhood of the strike is a significant contributing factor. In the case of multi-fin FinFETs, the charge collected per fin is seen to reduce as the number of fins increase. Thus, smaller FinFETs are susceptible to high amounts of charge collection.