# NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

## TL;DR

NullHop is a flexible CNN accelerator that leverages neuron activation sparsity to improve power efficiency and reduce computation time, suitable for low-power, low-latency applications, and demonstrated on FPGA with high efficiency.

## Contribution

The paper introduces NullHop, a novel FPGA-based CNN accelerator that exploits sparsity for efficiency and flexibility across various kernel sizes, outperforming traditional GPU implementations.

## Key findings

- Achieves over 450 GOp/s on VGG19 in simulations.
- Power efficiency exceeds 3 TOp/s/W.
- Maintains over 98% MAC unit utilization.

## Abstract

Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though Graphical Processing Units (GPUs) are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from 1x1 to 7x7. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq FPGA platform and present results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Post-synthesis simulations using Mentor Modelsim in a 28nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the MAC units, and achieves a power efficiency of over 3TOp/s/W in a core area of 6.3mm$^2$. As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real time interactive demonstrations.