# On the Scalability of Data Reduction Techniques in Current and Upcoming HPC Systems from an Application Perspective

## TL;DR

This paper investigates data reduction techniques in HPC systems, analyzing their scalability and proposing multi-threaded data transformations to improve I/O performance in particle-in-cell simulations.

## Contribution

It introduces a scaling law for data reduction bottlenecks and implements multi-threaded data transformations in ADIOS to enhance I/O efficiency on heterogeneous HPC systems.

## Key findings

- Identified throughput and I/O size as key bottlenecks.
- Developed a scaling law for data reduction performance.
- Validated multi-threaded data transformations for reduced I/O latency.

## Abstract

We implement and benchmark parallel I/O methods for the fully-manycore driven particle-in-cell code PIConGPU. Identifying throughput and overall I/O size as a major challenge for applications on today's and future HPC systems, we present a scaling law characterizing performance bottlenecks in state-of-the-art approaches for data reduction. Consequently, we propose, implement and verify multi-threaded data-transformations for the I/O library ADIOS as a feasible way to trade underutilized host-side compute potential on heterogeneous systems for reduced I/O latency.