# Integer Echo State Networks: Efficient Reservoir Computing for Digital Hardware

## TL;DR

This paper introduces integer Echo State Networks (intESN), a hardware-efficient reservoir computing model using integer vectors and cyclic shifts, achieving high energy efficiency with minimal performance loss.

## Contribution

The paper presents a novel intESN architecture that replaces traditional matrix operations with cyclic shifts, enabling efficient digital hardware implementation.

## Key findings

- Significant reduction in memory footprint and computational complexity.
- Confirmed energy efficiency improvements on FPGA hardware.
- Maintained competitive performance on typical reservoir computing tasks.

## Abstract

We propose an approximation of Echo State Networks (ESN) that can be efficiently implemented on digital hardware based on the mathematics of hyperdimensional computing. The reservoir of the proposed integer Echo State Network (intESN) is a vector containing only n-bits integers (where n<8 is normally sufficient for a satisfactory performance). The recurrent matrix multiplication is replaced with an efficient cyclic shift operation. The proposed intESN approach is verified with typical tasks in reservoir computing: memorizing of a sequence of inputs; classifying time-series; learning dynamic processes. Such architecture results in dramatic improvements in memory footprint and computational efficiency, with minimal performance loss. The experiments on a field-programmable gate array confirm that the proposed intESN approach is much more energy efficient than the conventional ESN.