Design and implementation of dynamic logic gates and R-S flip-flop using quasiperiodically driven Murali-Lakshmanan-Chua circuit

TL;DR

This paper demonstrates how a quasi-periodically driven Murali-Lakshmanan-Chua circuit can be used to implement dynamic logic gates and R-S flip-flops, with experimental, numerical, and analytical validation.

Contribution

It introduces a novel method to realize multiple logic gates and flip-flops within a single circuit system using threshold-based signal propagation.

Findings

Signal propagation occurs above a threshold amplitude.

Single circuit can produce complementary logic gates simultaneously.

Cross-coupled circuits mimic R-S flip-flop dynamics.

Abstract

We report the propagation of a square wave signal in a quasi-periodically driven Murali-Lakshmanan-Chua (QPDMLC) circuit system. It is observed that signal propagation is possible only above a certain threshold strength of the square wave or digital signal and all the values above the threshold amplitude are termed as 'region of signal propagation'. Then, we extend this region of signal propagation to perform various logical operations like AND/NAND/OR/NOR and hence it is also designated as the 'region of logical operation'. Based on this region, we propose implementing the dynamic logic gates, namely AND/NAND/OR/NOR, which can be decided by the asymmetrical input square waves without altering the system parameters. Further, we show that a single QPDMLC system will produce simultaneously two outputs which are complementary to each other. As a result, a single QPDMLC system yields either AND as well as NAND or OR as well as NOR gates simultaneously. Then we combine the corresponding two QPDMLC systems in a cross-coupled way and report that its dynamics mimics that of fundamental R-S flip-flop circuit. All these phenomena have been explained with analytical solutions of the circuit equations characterizing the system and finally the results are compared with the corresponding numerical and experimental analysis.

Equations

$$C\frac{dv}{dt}$$

$$L\frac{d{i}_L}{dt}$$

$$g(v)=\left\{\begin{array}[]{ll}m_{0}v+(m_{0}-m_{1})B_{p},&v<-B_{p},\\ m_{1}v,&-B_{p}\leq v\leq B_{p},\\ m_{0}v+(m_{1}-m_{0})B_{p},&v>B_{p}.\end{array}\right.$$

$$\dot{x}=y-h(x),$$

$$\dot{y}=-\beta (1+\nu )y-\beta x+F_1\sin ({\omega }_{1}t)+F_2\sin ({\omega }_{2}t),$$

$$h(x)=\left\{\begin{array}[]{ll}bx+(a-b),&x>1,\\ ax,&|x|\leq 1,\\ bx-(a-b),&x<-1,\end{array}\right.$$

$$\dot{x}$$

$$\dot{y}$$

$$y(t)$$

$$x(t)$$

$$C_{0,\pm }^{\prime 1}$$

$$C_{0,\pm }^{\prime 2}$$

$${\nu }_1+{\nu }_1\le -{\delta }_T,$$

$${\nu }_1+{\nu }_2\le -{\delta }_T,$$

$${\nu }_2+{\nu }_2\ge {\delta }_T.$$

$${\nu }_1\le \frac{-3{\delta }_T}{2},$$

$${\nu }_2\ge \frac{{\delta }_T}{2},$$

$${\nu }_1+{\nu }_1\le -{\delta }_T,$$

$${\nu }_1+{\nu }_2\ge {\delta }_T,$$

$${\nu }_2+{\nu }_2\ge {\delta }_T.$$

$${\nu }_1\le \frac{-{\delta }_T}{2},$$

$${\nu }_2\ge \frac{3{\delta }_T}{2},$$

$${\dot{x}}_1$$

$${\dot{y}}_1$$

$${\dot{x}}_2$$

$${\dot{y}}_2$$

$$I(y_{1,2})=\left\{\begin{array}[]{ll}\frac{3y_{1,2}}{2},&y_{1,2}<0,\\ \frac{y_{1,2}}{2},&y_{1,2}>0.\\ \end{array}\right.$$

$$\ddot{y}+(\beta +\beta \nu +\mu )\dot{y}+(\beta +\mu \beta \nu +\beta \mu )y=\Delta +\mu F_1\sin ({\omega }_{1}t)$$

$$+{\omega }_1{F}_1\cos ({\omega }_{1}t)+\mu F_2\sin ({\omega }_{2}t)+{\omega }_2{F}_2\cos ({\omega }_{2}t),$$

$$y(t)$$

$$A$$

$$B$$

$${\alpha }_{1,2}$$

$$E_1$$

$$E_{12}$$

$$E_{13}$$

$$E_{22}$$

$$E_{23}$$

$$x(t)$$

$$C_{0,\pm }^1$$

Full text

Nonlinear dynamics based computing, Murali-Lakshmanan-Chua circuit, Quasi-periodicity, SNA, Logic gates, and R-S flip-flop

Nonlinear dynamics based computing is an emerging field which can replace silicon chips and is becoming increasingly popular in nonlinear and chaotic dynamics, and computing research. Actually, Boolean based silicon chips are extremely logical in their operations. These logical operations can be classified into two groups, namely combinational logic circuits and sequential logic circuits. The basic building blocks for combinational logic circuits are the logic gates, namely AND, OR, NOT, NAND, NOR, etc., whereas the basic building block for sequential logic circuits is the flip-flop. Here, we have proposed a new mechanism by using a quasi-periodically driven nonlinear dynamical system exhibiting a strange non-chaotic attractor for constructing the logic gates AND/NAND/OR/NOR and fundamental R-S flip-flop circuit with Murali-Lakshmanan-Chua circuit as an example. By only imposing constraints on the logic high and logic low values of the input signal, we are able to implement these dynamic logic gates and flip-flop. In fact, without altering the system parameters, we point out how the logical operations can be decided by the asymmetrical input square waves. Consequently, dynamic computing using the behaviour of nonlinear dynamical systems is shown to be quite implementable in hardware devices. Our results also show that nonlinearity is more significant than the existence of chaos for design of the logic gates and latches.

I Introduction

In recent years, there has been new theoretical directions in harvesting the richness of nonlinear dynamics based computing. In particular, the phenomenon of chaos can be exploited to do flexible computations. This so-called chaos computing paradigm is driven by the motivation to use a single chaotic unit to emulate different logic gates and ultimately construct a more dynamic architecture. In this direction, the pioneering work of Sinha and Ditto is based on the thresholding (clipping/limiter) method to implement different logic gates sinha:98:01 ; sinha:99:01 ; munakata:02:01 ; murali:03:01 . Then Prusha and Linder emphasized the importance of nonlinearity over chaos using a nonlinear paramaterized map and illustrated why chaos and computation require nonlinearity prusha:99:01 . Following this, Murali and Sinha proposed a different scheme, in particular using synchronization of a driver and response nonlinear system, to achieve logic gate operations murali:07:01 ; murali:09:01 ; koh:14:01 . Recently, Murali et al murali:07:01 ; murali:09:01 had shown that the interplay between a moderate noise floor and the nonlinearity can be exploited for the design of key logic gate structures termed as Logical Stochastic Resonance(LSR). This work was followed by Kohar et al to demonstrate that the noise in conjunction with a periodic drive yields a consistent logic gate structure for all noise strengths koh:14:01 . They also showed the existence of noise-free LSR by driving a bistable system gup:11:01 with periodic forcing. Consequently, nonlinear dynamics based computing has received much attention and it has been demonstrated over a variety of physical, chemical and biological systems prv:16:01 ; koh:12:01 ; wors:10:01 ; guer:10:01 ; sinha:09:01 ; zamora:10:01 . Besides, many of the recent works focussed on the possibility of utilizing a nonlinear system, not just as a logic gate but also as a memory device. In particular, Cafagna and Grassi proposed chaos based S-R flip-flop from two cross coupled NOR gates implemented by a single Chua’s circuit cafagna:06:01 . Campos-Canton et al canton:12:01 reported a reconfigurable analog block able to simulate different logic gates and S-R flip-flop with the logic output signal based on the equation of the plane in analytic geometry. They validated their results with experiments canton:12:01 . Kohar and Sudeshna Sinha demonstrated how noise allows a bistable system to behave as a Set-Reset latch as well as a logic gate koh:12:01 . Nan Wang and Aiguo Song obtained Set-Reset latch logic operation in a symmetric bistable system subject to colored noise nan:14:01 . Apart from logic gates and memory device, Campos-Canton et al have proposed a parameterized method to design all multivibrator circuits via chaotic Chua circuit system. These authors have electronically realized all multivibrator circuits, pulse generator and a full S-R flip-flop device canton:12:02 .

Recently, two of the present authors described the implementation of dynamic logic gates using Logical Vibrational Resonance(LVR) by driving a piecewise linear non-autonomous system with periodic forcing prv:16:02 . On employing a second harmonic perturbation to a periodically driven nonlinear system to exhibit the vibrational resonance phenomenon, it has been found greb:84:01 ; gopa:13:01 ; ditt:90:01 ; tham:06:01 ; ven:99:01 ; ven:00:01 ; ven:01:01 ; prasad:97:01 ; feud:06:01 ; kapit:93:01 that if the frequency of the second harmonic force and the driving force are incommensurate, then their ratio will be irrational and one can find the occurrence of strange non-chaotic attractors (SNAs) in these systems. Such systems are designated as quasiperiodically driven nonlinear systems (QPDNS). Though quasiperiodically driven nonlinear systems are ubiquitous, widespread and are observed in numerous physical, and biological situations feud:06:01 ; kapit:93:01 , one can make use of them to propagate signals, and to design and implement dynamic logic gates, and flip-flop operations using certain nonlinear circuits. Operating the circuit in a SNA regime exploits needed nonlinearity without the exponential divergence of nearby trajectories associated with chaos. As a result, robust nonlinear dynamics based computing is possible against noise. So far, to our knowledge, quasiperiodically driven nonlinear systems exhibiting SNAs have not been used in the literature to achieve nonlinear dynamics based computing. In this paper, we first make use of a quasi-periodically driven Murali-Lakshmanan-Chua (QPDMLC) circuit system to enhance nonlinear dynamics based computing.

In all the previous studies of nonlinear dynamics based computing, the two logical inputs that are to be logically added are considered either as perturbations on the potential well using current sources or as external perturbations using voltage sources for building logic gates. Apart from these, to get the desired logic behavior, one has to change either the system parameters or include an asymmetry bias on nonlinear systems exhibiting phenomena like chaos synchronization, threshold mechanism, and stochastic resonance. Recently a new mechanism was proposed to get dynamic logic gates by imposing constraints on the high ($1$) and low ([math]) states of the logical inputs in Logical Vibrational Resonance Murali-Lakshmanan-Chua circuit system prv:16:02 . In this mechanism, there is no need to alter either the system parameters or add external asymmetry bias to get dynamic logic behavior. Hence, it is easier to design dynamic logic gates through this method rather than with the other techniques because the amplitudes of the two square waves or digital signals will be the deciding factor for the dynamic gates.

In this paper, we make use of the mechanism proposed by two of the present authors prv:16:02 and modify it to yield conditions for AND/NAND and OR/NOR gates to meet our needs for building dynamic logic gates. The reason to modify the above mechanism is due to the availability of different selective bounded AND, OR and NOT response regions in the two parameter phase diagram. As a result, to select any logical operation, one has to change not only the amplitude of the second harmonic force but also the amplitude of the positive or high state input logical signal. However, this is not required in the present paper, where the asymmetric amplitudes of logical input alone will be the deciding factor for different logical behaviors. This is due to the occurrence of selective bounded and same response regions which correspond to AND and OR operations, respectively, in the two parameter diagram. Apart from this, we have also reported that the single QPDMLC system can logically add the given two logical inputs and yield not only logical AND or OR via x variable, but also provide its complement, that is NAND or NOR, through y variable simultaneously. Thus, we first demonstrate in an electronic circuit in which the occurrence of parallel implementation of logic gates can be implemented. By using this parallelism inherent in this circuit, we obtain active high R-S flip-flop and active low R-S flip-flop from the two cross-coupled QPDMLC circuit. These kind of results have not been observed in any of the previous studies.

However, the success of nonlinear dynamics based computing is based on the fact that how far the given square wave or digital signal is propagated by the nonlinear system under various phenomena like stochastic resonance and vibrational resonance raja:16:01 . Taking into account these considerations, we evaluated the threshold amplitude for the input square wave or digital signal to be propagated by the QPDMLC system. The region above the threshold amplitude called the ‘region of signal propagation’ is depicted in a two parameter phase diagram. From the region of signal propagation, we determine the conditions for logic high or positive peak and logic low or negative peak inputs to get the desired AND/OR and NAND/NOR behaviors simultaneously. Further, we extend this idea to implement the fundamental R-S flip-flop by combining two QPDMLC systems operating in the NAND gate mode which is simpler to understand. All these phenomena have been explained by the analytical solution to the normalized circuit equation of the MLC circuit with an incommensurate frequency second harmonic driving force and the results are compared with the numerical solutions obtained by solving the normalized circuit equations using the Runge-Kutta fourth order method. Thus, we have succeeded in designing the desired dynamic computing elements, namely the dynamic logic gates and R-S flip-flop, via the QPDMLC system without altering the system parameters and are able to prove that the amplitudes of the logic high and low states are the deciding factors for dynamic computing.

The structure of the paper is as follows. In Sec.II, the circuit realization of QPDMLC system has been discussed and its solutions are analytically derived (see Appendix A). In Sec.III, we have successfully explained the possibility of propagation of the square wave or digital signal via QPDMLC through a two parameter phase diagram using the analytical as well as numerical solutions. Following this we have discussed the analytical, numerical and experimental implementation of logic gates and R-S Flip-flop using the QPDMLC system in Sec. IV and Sec. V, respectively.

II Circuit realization of quasi-periodically driven Murali-Lakshmanan-Chua system

Let us consider a simple electronic circuit corresponding to a quasi-periodically driven Murali-Lakshmanan-Chua (QPDMLC) ven:99:01 ; murali:94:01 ; murali:93:01 ; laks:03:01 ; laks:96:01 circuit system as shown in Fig. 1.

By applying Kirchoff’s law, the dynamical equations can be represented as follows:

[TABLE]

where $v$ and $i_{L}$ are the voltage across capacitor C, and current through the inductor L, respectively in the nonlinear system, while $f_{1}$ and $f_{2}$ are the strengths of the external periodic voltage sources of frequencies $\Omega_{1}$ and $\Omega_{2}$, respectively. Here $g(v)$ represents the piecewise-linear characteristic function of Chua’s diode in the system:

[TABLE]

In eq. (2), $m_{0}$ and $m_{1}$ are the inner and outer slopes of the $(v-i)$ characteristic curve of the Chua’s diode, respectively, and $B_{p}$ is the break point which distinguishes the inner and outer slopes of the $(v-i)$ curve. For analytical and numerical confirmation we rescale Eqs. (II) by redefining $v=xB_{p}$, $i_{L}=yGB_{p}$, $G=1/R$, $\omega_{1}=\Omega_{1}C/G$, $\omega_{2}=\Omega_{2}C/G$, $t=\tau C/G$ and $\tau$ as $t$. The set of normalized equations obtained after rescaling are as follows:

[TABLE]

where the overdot indicates the time differentiation and

[TABLE]

and $\beta=C/LG^{2}$, $\nu=GR_{s}$, $F_{1/2}=f_{1/2}\beta/B_{p}$, $a=G_{a}/G$, $b=G_{b}/G$, $G_{a}=m_{1}=-0.76~{}ms$, $G_{b}=m_{0}=-0.41~{}ms$ and $B_{p}=1V$. The parameters are fixed at $a=-1.02$, $b=-0.55$, $\nu=0.015$, $\beta=1.0$, $\omega_{1}=2.0$. To investigate the system under quasi-periodic forcing, the frequency of the second harmonic force is kept as $\omega_{2}=\frac{\sqrt{5}-1}{2}$ to meet the requirement that the ratio of the frequencies $\frac{\omega_{1}}{\omega_{2}}$ is irrational. The analytical solutions of the above system (3) has been discussed briefly in Appendix A.

III Propagation of square wave signal through Quasi-periodically driven Murali - Lakshmanan - Chua circuit system

In order to propagate the digital signal, a voltage source or square wave signal represented by $I^{\prime}$ (which is to be designated as I after rescaling, $I=I^{\prime}\beta/B_{p}$, in the normalized equations) is added in series with the external driving force as shown in Fig. LABEL:mlc_sna_signal. After applying Kirchoff’s law and rescaling, the set of normalized equations become

[TABLE]

The corresponding solutions are given by

[TABLE]

and

[TABLE]

where $E^{\prime}_{1}=\frac{\mu I+\Delta}{B}$ and the integrating constants become

[TABLE]

[TABLE]

Choosing the initial conditions as $x_{0}=0.2$, $y_{0}=0.3$ at $t_{0}=0$, we fix $F_{1}=0.08$. Thus, for various values of $F_{2}$ in the range [math] to $0.2$, different amplitudes ($\delta$) of the square wave signals are employed in the QPDMLC system (5). On evaluating the solutions x and y of the system (5) by using Eqs.(7) and (6), it has been found that only for a critical value or above the amplitude ($\delta$) of the square wave signal alone it will be propagated by the QPDMLC system through its state variables x and y. For all other values of $\delta$ (that is lower than the critical value for fixed $F_{2}$ value), the state variable x of the system is either in $x>0$ (logic high state) region or in $x<0$ (logic low state) region or in the bistable region. Further, the state variable y of the system is always found to be complementary to the state variable x.

Without loss of generality, for the random input square wave or digital signal, the logical high ($1$) state is taken as $+\delta$ and logical low ([math]) state as $-\delta$. Then, the nature of the state variables x and y are analyzed using Eqs.(7) and (6) and they are plotted in two parameter phase diagrams as shown in Figs. 3(a) and 3(b), respectively. The state variable x of the system (5) mimics the input square wave or digital signal such that the logic high input is obtained at the output as $x>0$ and logic low input is obtained as $x<0$ at the output. This type of response of the QPDMLC system (5) for the random input square wave or digital signal corresponds to the red region of the two parameter phase diagram as shown in Fig. 3(a). Hence, this region is called the signal propagation region. On the other hand, in Fig. 3(a), the green region corresponds to the logical output response $0-$ state, that is $x<0$, the blue region corresponds to the logical output response $1-$ state, that is $x>0$, and the pink region corresponds to the bistable state ($x>0$ and $x<0$) irrespective of the states of the digital input signal. Thus, we interpret the output state of QPDMLC system $x(or~{}y)<0$ as logic low output [math] and the state $x(or~{}y)>0$ as logic high output $1$ throughout our discussion.

On the other hand, the corresponding state variable y of the same system mimics the inverted input square wave or digital signal which corresponds to the red region, while the green region corresponds to the logical output response $0-$ state, that is $y<0$, while the blue region corresponds to the logical output response $1-$ state, that is $y>0$, and the pink region corresponds to the bistable state irrespective of the logical states of the input signal as shown in Fig. 3(b).

Numerical simulations of the system (5) has been performed using the Runge-Kutta fourth (RK IV) order algorithm. The different responses (state variables x and y) of the system to the random digital input signal are plotted as two parameter phase diagrams as in Figs. 3(c) and 3(d), respectively, which are found to be in complete agreement with the analytical results.

Finally, the above behaviors have been further confirmed for the random signal propagation (see Fig. 4(a)) with amplitude $\delta=0.006$ by choosing different $F_{2}$ values in different regions of the two parameter phase diagram for different time intervals. They are plotted in Fig. 4(b)(red line represents x state variable and green line represents y state variable) using the analytical solution. It has been found that for the interval $[0:1.0~{}s]$, choosing $F_{2}=0.01$ (blue region in the two parameter phase diagram (see Fig. 3(a)) using the state variable x and green region in the two parameter phase diagram (see Fig. 3(b)) using the state variable y), the state of the QPDMLC system x is found to be always in the logic low state ($x<0$) and y is in the logic high state ($y>0$) irrespective of the state of the inputs $+\delta$ or $-\delta$. On the other hand, for the interval $[1.0:2.0~{}s]$ with $F_{2}=0.04$ (red region in Figs. 3(a) and 3(b)), the system state variable x mimics the input state which confirms the signal propagation and the system state variable y mimics the inverted input state which confirms the inverted signal propagation, respectively. Then for the interval $[2.0:3.0~{}s]$ with $F_{2}=0.16$ (the pink region in Figs. 3(a) and 3(b)), the system states x and y are in a bistable state. Fig. 4(c) is obtained by numerical method which also confirms these behaviors.

IV Implementation of logic gates via QPDMLC circuit

The combinational logic circuit element or logic gate is composed of strange non-chaotic non-linear system, namely the MLC system with an external incommensurate frequency driving force and two random pulsed voltage sources $I^{\prime}_{1}$ and $I^{\prime}_{2}$ instead of a single voltage source $I^{\prime}$ shown in Fig. LABEL:mlc_sna_signal. As pointed out by Venkatesan, Murali and Lakshmanan ven:99:01 , the parameters of the QPDMLC circuit system is set to exhibit a strange non-chaotic attractor (SNA) by choosing $F_{1}=0.08$ and $F_{2}=0.07454785$ throughout our discussion for the nonlinear dynamics based computing. In order to perform the logical operations, one must have at least two input signals. Hence, the two voltage sources $I_{1}$ and $I_{2}$ serve this purpose and after rescaling they will become $I_{1}+I_{2}$ instead of $I$ in Eqs.  (5b), (6), (7), (8), and  (9), respectively.

With these input signals, the four possible input combinations $(0,0)$, $(0,1)$, $(1,0)$, $(1,1)$ are merged into three different input combinations $(0,0)$, $(0,1)/(1,0)$ and $(1,1)$. The low input is taken as $\nu_{1}$ for logical [math] and the high input as $\nu_{2}$ for logical $1$. With no loss of generality, consider the two inputs $I_{1}$ and $I_{2}$ to take the value $\nu_{1}$ when the logic input is [math], and the value $\nu_{2}$ when the logic input is $1$. Then, the two logical inputs are logically added for different combinations either by AND or by OR manner so as to yield the resultant which is either a logic low output [math] which corresponds to a value less than or equal to $-\delta_{T}$ or a logic high output $1$ corresponding to a value greater than or equal to $\delta_{T}$. The polarity of $\delta_{T}$ specifies either the system resides in a positive potential well or a negative potential well. Further, $\delta_{T}$ is the amplitude of the digital input signal to be propagated by the QPDMLC system discussed in the previous section. As a result, the value of $\delta_{T}$ and $F_{2}$ will always be chosen in the signal propagation region of QPDMLC system shown in the two parameter phase diagram (red region in Fig. 3(a)) corresponding to the state variable x. Let the system parameters be chosen as $\delta_{T}=0.05$ and $F_{2}=0.07454785$. This is because the parameters in this region alone make the QPDMLC system to logically add the given two inputs and finally yield an output that is similar to either AND or OR gate operation. Hence, this region can also be named as ‘region of logical operation’. With these considerations the three possible input combinations are added logically either as AND or as OR manner and the resultant should necessarily satisfy the signal propagation condition (or the resultant $\delta_{T}$ value should necessarily lie on the red region or signal propagation region or logical operation region of the two parameter phase diagram corresponding to x state variable) as follows:

AND Gate:

[TABLE]

From Eq.(10c), $\nu_{2}\geq\frac{\delta_{T}}{2}$. On substituting in Eq.(10b), $\nu_{1}\leq\frac{-3\delta_{T}}{2}$ which also satisfies Eq.(10a). Thus,

[TABLE]

are the conditions for AND operation.

OR Gate:

[TABLE]

With Eq.(12a) , $\nu_{1}\leq\frac{-\delta_{T}}{2}$. On substituting in Eq.(12b), $\nu_{2}\geq\frac{3\delta_{T}}{2}$ which also satisfies Eq.(12c). Thus

[TABLE]

are the conditions for OR operation.

As an example, let us fix the parameters, $F_{1}=0.08$, $F_{2}=0.07454785$ and $\delta_{T}=0.05$ in the propagation region (red region) of the two parameter phase diagram shown in Fig. 3(a). As a result, the low ($\nu_{1}$) and high ($\nu_{2}$) states of the input signal become $\nu_{1}=-0.075$ and $\nu_{2}=0.025$, respectively for AND/NAND operation from Eq. (11). Similarly, Eq. (13) results in $\nu_{1}=-0.025$ and $\nu_{2}=0.075$, respectively, for OR/NOR operation. With these values, for the various logical input combinations $(\nu_{1},\nu_{1})$, $(\nu_{1},\nu_{2})$, $(\nu_{2},\nu_{1})$, and $(\nu_{2},\nu_{2})$, the state variable x of the QPDMLC system mimics AND, and y mimics NAND operations simultaneously as shown in Fig. 5. Similarly, for various combinations of $\nu_{1}=-0.025$ and $\nu_{2}=0.075$, the system shows the OR and NOR response as in Fig. 2.

IV.1 Experimental investigation

The dynamics of the QPDMLC system, namely, the MLC system with an external incommensurate frequency driving force with two square pulses $I^{\prime}_{1}$ and $I^{\prime}_{2}$ instead of a single input square pulse $I^{\prime}$ [see Fig. 1] has been investigated experimentally. To confirm our numerical results through experimental study of the circuit given in Fig2. LABEL:mlc_sna_signal, the circuit parameters corresponding to the dimensionless units of parameters used in our above numerical studies are fixed at $C=10nF$, $L=18mH$, $R=1340ohms$, $R_{s}=20ohms$, $\gamma_{1}(=\frac{\Omega_{1}}{2\pi})=23706.667Hz$ and $\gamma_{2}(=\frac{\Omega_{2}}{2\pi})=7325.763Hz$, $f_{1}=0.056572V_{rms}$ and $f_{2}=0.05270V_{rms}$. For this set of system parameter values, it has already been observed that the circuit exhibits strange non-chaotic behaviour ven:99:01 . Now, under the influence of two inputs, $I^{\prime}_{1}$ and $I^{\prime}_{2}$, the change in the time series of the attractor is obtained by measuring the voltage ‘$v$’ across the capacitor ‘$C$’ and the current $i_{L}$ through the inductor ‘$L$’ in the form of voltage drop across the current sensing resistor ‘$R_{s}$’ ($v_{s}=R_{s}i_{L}$). The two inputs $I^{\prime}_{1}$ and $I^{\prime}_{2}$ and the voltages ‘$v$’ and ‘$v_{s}$’ are connected to the channels $1,2,3$ and $4$ of the Agilent Mixed Storage Oscilloscope (MSO-X 3014A). Then, for the two appropriate asymmetric input square waves, the response of the QPDMLC system exhibits AND gate (in the ‘$v$’ variable) and NAND gate (in the ‘$v_{s}$’ variable) (see Fig. 7). For another set of two appropriate asymmetric input square waves, the system behaves as OR gate (when we measure the voltage across ‘$C$’) and NOR gate (when we measure the voltage across ‘$R_{s}$’) (see Fig. 8). Thus the parallelism of AND and NAND as well as OR and NOR are inherent in the QPDMLC circuit, which will help to perform the logic operations faster.

V Implementation of R-S flip-flop via QPDMLC circuit

Next we consider a system of two QPDMLCs mimicking AND/NAND gates are coupled to form a basic building block for sequential logic circuit, which is termed as a Flip-Flop circuit. Thus, the two coupled QPDMLC circuit systems characterizing an active high as well as active low R-S flip-flop is represented as follows:

[TABLE]

where

[TABLE]

The solution of the above characteristic equations is found to be similar to the solution of individual QPDMLC system (5) just by modifying the constant I by $R+I(y_{1})$ and $S+I(y_{2})$, respectively. Thus, the solutions $x_{1,2}$ and $y_{1,2}$ are obtained from Eqs. (7) and (6) by replacing I by $S+I(y_{2})$ and $R+I(y_{1})$, respectively, and one can plot the response of the coupled system (V) as shown in Fig. 6(b). Here, we interpret $y_{1}$ as the output $Q$ and $y_{2}$ as the output $\bar{Q}$ of the R-S flip-flop. Also, the state variables $y_{1,2}>0$ are taken as the logical high output and $y_{1,2}<0$ are taken as the logical low output. Finally, the various operations of the active high R-S flip-flop are described as follows:

$1$. When S and R inputs are both $\nu_{1}=-0.075$ or low, the outputs $y_{1}$ and $y_{2}$ simultaneously go to the logical low ([math]) or $y_{1,2}<0$. This represents the prohibited or forbidden state for the flip-flop.

$2$. When S is $\nu_{1}=-0.075$ or low and R is $\nu_{2}=0.025$ or high, the $y_{1}$ output is set to the logical high ($1$) or $y_{1}>0$ and $y_{2}$ output is reset or cleared to low ([math]) or $y_{2}<0$. This mimics the set condition.

$3$. When S is $\nu_{2}=0.025$ or high and R is $\nu_{1}=-0.075$ or low, the $y_{1}$ output is reset to the logical low ([math]) or $y_{1}<0$ and $y_{2}$ output is set to high ($1$) or $y_{2}>0$. This mimics the reset condition.

$4$. When S and R inputs are both $\nu_{2}=0.025$ or high, the coupled QPDMLC system leaves the outputs $y_{1}$ and $y_{2}$ in their previous complementary states. This shows the condition for holding or idle or rest or memory effect.

Similarly the response of the state variables $x_{1}$ taken as $Q^{\prime}$ and $x_{2}$ taken as $\bar{Q^{\prime}}$ are shown in Fig. 7(b) which is designated as active low R-S flip-flop. It is found that the set and the reset conditions are interchanged for the state variables $x_{1,2}$. The above results are verified numerically using the Runge-Kutta fourth order method and plotted in Figs. 6(c) and 7(c) for the state variables $y_{1,2}$ and $x_{1,2}$, respectively.

VI Conclusions

In summary, we have deduced the equations for a quasi-periodically driven Murali-Lakshmanan-Chua system which mimics dynamic logic gates and fundamental R-S flip-flop and an exact analytic solution has been given. Further, we have shown the propagation of square waves or digital signals through the quasi-periodically driven Murali-Lakshmanan-Chua circuit system is possible for certain regions named as signal propagation region in the two parameter phase diagram. We have extended this idea of signal propagation to construct the basic building blocks for combination logic circuits, namely logic gates, and basic building block for sequential logic circuit, namely flip-flop. In particular, we have shown the direct and flexible implementation of the desired basic logic gates OR / NOR as well as AND / NAND using the QPDMLC system by properly choosing the values of logic high and logic low inputs which are designated as the asymmetrical input signals. These asymmetrical amplitudes for positive and negative states of the input signal are obtained by the conditions for AND and OR gates using the parameters $\delta$ and $F_{2}$ in the signal propagation region of the two parameter phase diagram. Later, we have extended this idea to implement the active high R-S flip-flop and active low R-S flip-flop simultaneously, by combining the two QPDMLC systems under AND/NAND conditions. All these behaviors are studied by analytical method and verified with the numerical results. The logic gates have also been experimentally realized. It has been concluded that all these dynamic computings are done without altering the system parameters which in turn depends on the asymmetrical amplitudes of the input square wave signals. Such a scheme of implementation of basic dynamic logic gates and flip-flop for digital circuits may serve as ingredients of a general purpose device more flexible than statically wired hardware.

VII Acknowledgements

The authors thank the reviewers for their valuable suggestions. The authors would like to thank Dr. K.Murali and Dr. K.Srinivasan for their help in implementing the experiments. The work of ML was supported by NASI Platinum Jubilee Senior Scientist Fellowship.

Appendix A Analytical solutions for the quasi-periodically driven MLC Circuit

The system (3) can be explicitly integrated in terms of elementary functions in each of the three regions $D_{0}$, $D_{+}$ and $D_{-}$ ($|x|\leq 1$, $x>1$ and $x<-1$) separately and matched across the boundaries to obtain the full solution as shown below laks:03:01 .

It is found that in each one of the regions $D_{0}$, $D_{+}$ and $D_{-}$, the system (3) can be represented as a single second order inhomogeneous linear differential equation for the variable $y(t)$,

[TABLE]

where

$\mu=a$, $\Delta=0$ in region $D_{0}$,

$\mu=b$, $\Delta=\pm\beta(a-b)$ in region $D_{\pm}$ .

The general solution of the system  (3) can be written as

[TABLE]

where $C^{1}_{0,\pm}$ and $C^{2}_{0,\pm}$ are integration constants in the appropriate regions $D_{0}$, $D_{\pm}$, and

[TABLE]

Knowing $y(t)$ and substituting for $y$, $\dot{y}$ from Eq.(16), the value of $x(t)$ is obtained from Eq. (3b) and is found to be

[TABLE]

where $\sigma=\beta(1+\nu)$ and the values of the integration constants, namely $C^{1}_{0,\pm}$ and $C^{2}_{0,\pm}$, are obtained by substituting the initial condition at $t=t_{0}$, $x(t_{0})=x_{0}$ and $y(t_{0})=y_{0}$ in Eqs. (16) and (18). On solving further, the values of the constants are found as

[TABLE]

[TABLE]