Is error detection helpful on IBM 5Q chips ?

TL;DR

This paper demonstrates that implementing error detection and fault-tolerant design on IBM 5Q quantum chips improves sampling tasks, indicating that fault-tolerant quantum computation is practically achievable with current technology.

Contribution

The study provides experimental evidence that error detection enhances performance on IBM 5Q chips, supporting the feasibility of fault-tolerant quantum computing with existing hardware.

Findings

Average improvement in sampling tasks with fault-tolerant techniques

Evidence that fault-tolerant quantum computation is within reach

Validation of error detection benefits on real quantum hardware

Abstract

This paper reports on experiments realized on several IBM 5Q chips which show evidence for the advantage of using error detection and fault-tolerant design of quantum circuits. We show an average improvement of the task of sampling from states that can be fault-tolerantly prepared in the $[[4,2,2]]$ code, when using a fault-tolerant technique well suited to the layout of the chip. By showing that fault-tolerant quantum computation is already within our reach, the author hopes to encourage this approach.

Tables

Initial state	Unitary	Final state	# Instructions
$|00⟩$	$\mathrm{𝟙}\otimes \mathrm{𝟙}$	$|00⟩$	5
$|0+⟩$	$\mathrm{𝟙}\otimes \mathrm{𝟙}$	$\frac{|00⟩+|01⟩}{\sqrt{2}}$	6
$|00⟩$	$\mathrm{𝟙}\otimes X$	$|01⟩$	6
$|00⟩$	$X\otimes \mathrm{𝟙}$	$|10⟩$	6
$\frac{|00⟩+|11⟩}{\sqrt{2}}$	$\mathrm{𝟙}\otimes \mathrm{𝟙}$	$\frac{|00⟩+|11⟩}{\sqrt{2}}$	7
$|0+⟩$	$\mathrm{𝟙}\otimes Z$	$\frac{|00⟩-|01⟩}{\sqrt{2}}$	7
$|00⟩$	$H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩+|01⟩+|10⟩+|11⟩}{2}$	7
$|0+⟩$	$X\otimes \mathrm{𝟙}$	$\frac{|10⟩+|11⟩}{\sqrt{2}}$	7
$|00⟩$	$X\otimes X$	$|11⟩$	7
$\frac{|00⟩+|11⟩}{\sqrt{2}}$	$\mathrm{𝟙}\otimes Z$	$\frac{|00⟩-|11⟩}{\sqrt{2}}$	8
$\frac{|00⟩+|11⟩}{\sqrt{2}}$	$X\otimes \mathrm{𝟙}$	$\frac{|10⟩+|01⟩}{\sqrt{2}}$	8
$|00⟩$	$\mathrm{𝟙}\otimes Z\cdot H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩-|01⟩+|10⟩-|11⟩}{2}$	8
$|00⟩$	$Z\otimes \mathrm{𝟙}\cdot H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩+|01⟩-|10⟩-|11⟩}{2}$	8
$|0+⟩$	$X\otimes Z$	$\frac{|10⟩-|11⟩}{\sqrt{2}}$	8
$\frac{|00⟩+|11⟩}{\sqrt{2}}$	$\mathrm{𝟙}\otimes ZX$	$\frac{|10⟩-|01⟩}{\sqrt{2}}$	9
$|00⟩$	$Z\otimes Z\cdot H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩-|01⟩-|10⟩+|11⟩}{2}$	9
$|00⟩$	$CZ\cdot H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩+|01⟩+|10⟩-|11⟩}{2}$	10
$|00⟩$	$CZ\cdot \mathrm{𝟙}\otimes Z\cdot H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩-|01⟩+|10⟩+|11⟩}{2}$	11
$|00⟩$	$CZ\cdot Z\otimes \mathrm{𝟙}\cdot H\otimes H\cdot \mathrm{SWAP}$	$\frac{|00⟩+|01⟩-|10⟩+|11⟩}{2}$	11
$|00⟩$	$\mathrm{𝟙}\otimes X\cdot CZ\cdot H\otimes H\cdot \mathrm{SWAP}\cdot X\otimes \mathrm{𝟙}$	$\frac{|00⟩-|01⟩-|10⟩-|11⟩}{2}$	12

Implementation	Avg.Perf.($\times {10}^{-2}$)	Post-selection ratio
Bare[1-0]	$6.72$	$1.00$
Bare[2-0]	$5.50$	$1.00$
Bare[2-1]	$6.49$	$1.00$
Bare[2-4]	$6.98$	$1.00$
Bare[3-2]	$6.27$	$1.00$
Bare[3-4]	$7.73$	$1.00$
FTv1	$4.51$	$0.65$
NFT	$6.05$	$0.71$

chip	Temperature ($\mathrm{mK}$)
Raven	21
Sparrow	19

qubit	gate error (%)	$\sigma \left[\text{gate error}\right]$	readout error (%)	$\sigma \left[\text{readout error}\right]$
Q0	$0.1$	$0.021$	$4.1$	$0.63$
Q1	$0.08$	$0.035$	$4.7$	$0.96$
Q2	$0.15$	$0.024$	$2.7$	$0.36$
Q3	$0.15$	$0.016$	$6.2$	$1.11$
Q4	$0.19$	$0.026$	$5.1$	$1.1$

Equations

$${|00⟩}_{\mathrm{L}}$$

$${|01⟩}_{\mathrm{L}}$$

$${|10⟩}_{\mathrm{L}}$$

$${|11⟩}_{\mathrm{L}}$$

$$\Qcircuit@C=.5em@R=.5em{&\lstick{\mathrm{q_{1}}}\gate{H}\qw\\ \lstick{}\gate{H}\qswap\qw\raisebox{-25.00003pt}{$\equiv$}\lstick{\mathrm{q_{2}}}\gate{H}\qw\\ \lstick{}\gate{H}\qswap\qwx\qw\lstick{\mathrm{q_{3}}}\gate{H}\qw\\ \lstick{\mathrm{q_{4}}}\gate{H}\qw}$$

$$\Qcircuit@C=.5em@R=.5em{&\lstick{\mathrm{q_{1}}}\gate{S}\qw\\ \lstick{}\qw\ctrl{1}\qw\qw\raisebox{-25.00003pt}{$\equiv$}\lstick{\mathrm{q_{2}}}\gate{S}\qw\\ \lstick{}\gate{H}\targ\gate{H}\qw\lstick{\mathrm{q_{3}}}\gate{S}\qw\\ \lstick{\mathrm{q_{4}}}\gate{S}\qw}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\mathrm{q_{0}}\rightarrow\ket{0}}&\qw\targ\qw\qw\qw\qw\qw\targ\cw\\ \lstick{\mathrm{q_{1}}\rightarrow\ket{0}}\qw\qw\targ\qw\qw\qw\qw\qw\qw\qw\\ \lstick{\mathrm{q_{2}}\rightarrow\ket{0}}\gate{H}\ctrl{-2}\ctrl{-1}\gate{H}\targ\gate{H}\ctrl{2}\ctrl{-2}\qw\qw\\ \lstick{\mathrm{q_{3}}\rightarrow\ket{0}}\qw\qw\qw\gate{H}\ctrl{-1}\gate{H}\qw\qw\qw\qw\\ \lstick{\mathrm{q_{4}}\rightarrow\ket{0}}\qw\qw\qw\qw\qw\qw\targ\qw\qw\qw}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\ket{0}}&\qw\qw\qw\qw\qw\targ\targ\cw\\ \lstick{\ket{0}}\qw\qw\qw\targ\qw\qw\ctrl{-1}\qw\qw\\ \lstick{\ket{0}}\qw\targ\gate{H}\ctrl{-1}\qswap\ctrl{-2}\qw\qw\qw\\ \lstick{\ket{0}}\gate{H}\ctrl{-1}\gate{H}\ctrl{1}\qw\qwx\qw\qw\qw\qw\\ \lstick{\ket{0}}\qw\qw\qw\targ\qswap\qwx\qw\qw\qw\qw}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\mathrm{q_{0}}\rightarrow\ket{0}}&\qw\qw\qw\qw\qw\push{\rule{0.0pt}{10.00002pt}}\\ \lstick{\mathrm{q_{1}}\rightarrow\ket{0}}\qw\qw\qw\targ\qw\push{\rule{0.0pt}{10.00002pt}}\\ \lstick{\mathrm{q_{2}}\rightarrow\ket{0}}\qw\qw\targ\ctrl{-1}\qw\\ \lstick{\mathrm{q_{3}}\rightarrow\ket{0}}\gate{H}\ctrl{1}\ctrl{-1}\qw\qw\\ \lstick{\mathrm{q_{4}}\rightarrow\ket{0}}\qw\targ\qw\qw\qw}$$

$$S_{\mathrm{FT}}$$

$$G_{\mathrm{FT}}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{}&\qswap\qw\raisebox{-25.00003pt}{=}\ctrl{1}\gate{H}\ctrl{1}\gate{H}\ctrl{1}\qw\\ \lstick{}\qswap\qwx\qw\targ\gate{H}\targ\gate{H}\targ\qw\\ }$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\mathrm{q_{1}}\rightarrow\ket{0}}&\gate{H}\qw\qswap\qw\push{\rule{0.0pt}{10.00002pt}}\qw\\ \lstick{\mathrm{q_{2}}\rightarrow\ket{0}}\qw\targ\qswap\qwx\ctrl{2}\qw\\ \lstick{\mathrm{q_{3}}\rightarrow\ket{0}}\gate{H}\ctrl{-1}\qw\qw\qw\\ \lstick{\mathrm{q_{4}}\rightarrow\ket{0}}\qw\qw\qw\targ\qw}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\ket{0}}&\qw\targ\qw\\ \lstick{\ket{0}}\gate{H}\ctrl{-1}\qw\\ \lstick{\ket{0}}\gate{H}\ctrl{1}\qw\\ \lstick{\ket{0}}\qw\targ\qw}$$

$$D=\frac{1}{2}\Big{(}|p_{00}-\tilde{p}_{00}|+|p_{01}-\tilde{p}_{01}|+|p_{10}-\tilde{p}_{10}|+|p_{11}-\tilde{p}_{11}|\Big{)}.$$

$$\hat{D}=\frac{1}{2}\left(\left|p_{00}-\frac{n_{00}}{n_{\mathrm{valid}}}\right|+\left|p_{01}-\frac{n_{01}}{n_{\mathrm{valid}}}\right|+\left|p_{10}-\frac{n_{10}}{n_{\mathrm{valid}}}\right|+\left|p_{11}-\frac{n_{11}}{n_{\mathrm{valid}}}\right|\right),$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\mathrm{q_{0}}\rightarrow\ket{0}}&\qw\qw\qw\qw\qw\gate{H}\ctrl{2}\ctrl{1}\gate{H}\cw\\ \lstick{\mathrm{q_{1}}\rightarrow\ket{0}}\qw\qw\qw\qswap\qw\gate{H}\qw\targ\gate{H}\qw\qw\\ \lstick{\mathrm{q_{2}}\rightarrow\ket{0}}\qw\qw\targ\qswap\qwx\targ\gate{H}\targ\qw\gate{H}\qw\qw\\ \lstick{\mathrm{q_{3}}\rightarrow\ket{0}}\gate{H}\ctrl{1}\qw\qw\ctrl{-1}\qw\qw\qw\qw\qw\qw\\ \lstick{\mathrm{q_{4}}\rightarrow\ket{0}}\qw\targ\ctrl{-2}\qw\qw\qw\qw\qw\qw\qw\qw}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\mathrm{q_{1}}\ket{0}}&\qw\qw\qswap\qw\push{\rule{0.0pt}{10.00002pt}}\qw\\ \lstick{\mathrm{q_{2}}\ket{0}}\qw\targ\qswap\qwx\targ\qw\\ \lstick{\mathrm{q_{3}}\ket{0}}\gate{H}\ctrl{-1}\qw\qw\qw\\ \lstick{\mathrm{q_{4}}\ket{0}}\gate{H}\qw\qw\ctrl{-2}\qw}$$

$$\Qcircuit@C=.5em@R=.5em{\lstick{\ket{0}}&\gate{H}\ctrl{1}\qw\\ \lstick{\ket{0}}\qw\targ\qw\\ \lstick{\ket{0}}\gate{H}\ctrl{1}\qw\\ \lstick{\ket{0}}\qw\targ\qw}$$

Full text

Quantum Information and Computation, Vol. 0, No. 0 (0000) 000–000

©Rinton Press

IS ERROR DETECTION HELPFUL ON IBM 5Q CHIPS ?

CHRISTOPHE VUILLOTaaac.vuillot@tudelft.nl

1 - JARA Institute for Quantum Information, RWTH Aachen University

Physikzentrum Campus Melaten Otto-Blumenthal-Strasse, 52074 Aachen, Germany

2 - QuTech, TU Delft

Lorentzweg 1, 2628 CJ Delft, Netherlands

Received (received date)

Revised (revised date)

This paper reports on experiments realized on several IBM 5Q chips which show evidence for the advantage of using error detection and fault-tolerant design of quantum circuits. We show an average improvement of the task of sampling from states that can be fault-tolerantly prepared in the $[[4,2,2]]$ code, when using a fault-tolerant technique well suited to the layout of the chip. By showing that fault-tolerant quantum computation is already within our reach, the author hopes to encourage this approach.

Keywords: quantum, fault-tolerance, error detection, experiment

Communicated by: to be filled by the Editorial

1 Introduction

Quantum systems in laboratories around the world are reaching unprecedented level of control and precision for a variety of devices aiming at implementing reliable qubits. Yet, due to the very nature of those devices, errors are still notably present. In order to be able to execute long quantum algorithms, improvements should be made using quantum error correction and fault-tolerant schemes. So-called threshold theorems [1, 2] prove that there exist error rates below which this approach is guaranteed to improve the device performance. However, between those theorems and real experiments there remains a fog of technical details which clouds the actual practicality of error correcting codes.

Already some experiments which demonstrate the usefulness of quantum error correcting codes to protect a quantum memory have been done, e.g. [3, 4, 5, 6, 7], but a demonstration of protected computation is still missing.

Inspired by a recent proposal by D. Gottesman [8], we use an IBM 5Q chip to show that error detection can improve some simple sampling tasks, thus turning a tiny portion of fog into blue sky. Closely related to this work, [6] and [7] present experiments based on the same error detecting code, on trapped-ion qubits and on a similar superconducting chip, respectively. Both those works focus on the preparation of few states and only one of the two encoded qubits is handled fault-tolerantly. In this work an extensive set of fault-tolerant circuits is studied and both logical qubits are protected. Moreover [6] and [7] introduce artificial Pauli errors to study the robustness of their preparation whereas this work takes a higher level approach, treating the experimental set-up as a black box, probing only the intrinsic errors in the system. These considerations make the present work closer to the spirit of [8]. This work is, to the author’s knowledge, the first experimental demonstration of error detection and fault-tolerance improving a quantum computation.

The paper is organized as follows. In section 2 we present the principle of the approach and its specialization to the IBM 5Q chip. In section 3 the experimental results are shown and analyzed.

2 Demonstrating fault-tolerance

The idea behind fault-tolerance is to devise error correcting codes and the corresponding processes of encoding, correcting, computing or measuring with encoded information such that more errors are corrected than introduced [9]. The difficulty in devising such processes is that they are built out of components that are all faulty, so adding some might do more harm than it can help. Devising, proving and simulating fault-tolerant schemes has been pursued for the last 20 years, e.g. [9, 1, 10, 11, 12, 13, 14, 15], but improving and finding better schemes is still important and a subject of ongoing research, e.g. [16, 17, 18, 19, 20].

Taking one of these schemes and experimentally demonstrating its fault-tolerance, i.e finding an improvement of performance going from bare to encoded implementation, provides the ultimate validation of the scheme.

2.1 General approach

A description of a general approach to demonstrate fault-tolerant quantum computation is given in [8]; we just briefly recall it here. The idea is to choose a quantum error correcting code $\mathcal{C}$, admitting fault-tolerant circuits for the preparation of some logical states, denoted as $\ket{s_{1}},\dots,\ket{s_{m}}\in S_{\rm FT}^{\mathcal{C}}$, as well as for some logical quantum gates, denoted as $U_{1},\dots,U_{n}\in G^{\mathcal{C}}_{\rm FT}$. Using these as building blocks one can then randomly draw a state preparation from $S_{\rm FT}^{\mathcal{C}}$, then draw a sequence of gates from $G_{\rm FT}^{\mathcal{C}}$ to obtain an encoded fault-tolerant circuit.

More precisely, following the formalism of rectangles and extended rectangle introduced in [10], one interleaves the logical units (gates in $G^{\mathcal{C}}_{\rm FT}$, or preparation of states in $S^{\mathcal{C}}_{\rm FT}$) with a fault-tolerant circuit for error correction. Rectangles designate circuits comprising one logical unit preceded by a round of error correction, extended rectangles designate circuits comprising one logical unit preceded and followed by a round of error correction. The precise conditions to satisfy in order to be fault-tolerant for distance 3 codes are stated in [10]. This ensures that the whole computation is error free if there is at most one fault per extended rectangle.

The error model considered in this paper is that the failure of any component can introduce any Pauli error on the qubits acted on by the component. In our case, we cannot repeat fault-tolerant detection of errors, so our circuits will only tolerate a single fault in total.

The encoded circuits then have to be compared to a bare implementation on the physical qubits. Sampling from the final state produced by the circuit in the computational basis and comparing the probability distribution obtained with the expected one gives a simple comparison metric. Note that this supposes that the circuits are small enough or simple enough so that one can classically simulate sampling from the final state efficiently. A successful demonstration of fault-tolerant quantum computation happens if the encoded circuits show better performance than the bare circuits. To be the most convincing, one needs to use the best of the physical qubits as well as the most efficient implementation for the bare circuits.

2.2 The IBM 5Q chip and [[4,2,2]]

In 2016 IBM released a quantum chip with fixed-frequency superconducting transmon qubits, named IBM 5Q. They provide worldwide cloud access to the chip under an initiative called the “IBM Quantum Experience” [21]. The current iteration on which the experiments were done is nicknamed Raven. The appendix also presents and compares preliminary results obtained with a previous iteration, Sparrow. The chip has five qubits, natively named $q_{0}$ to $q_{4}$. It features single qubit Clifford gates, the $T$ gate ($\mathrm{diag}(1,\rm e^{i\pi/4})$) as well as some two-qubits CNOTs with a certain layout represented in Fig. 2.2a. This many qubits is the right number to use for a demonstration using the $[[4,2,2]]$ code as discussed in [8].

The $[[4,2,2]]$ code encodes two qubits into four physical qubits. Its code space is stabilized by the all-$X$ and all-$Z$ Pauli operators ($S_{X}=X\otimes X\otimes X\otimes X$, $S_{Z}=Z\otimes Z\otimes Z\otimes Z$), together with the logical Pauli operators, they are represented in Fig. 2.2b. The logical code states are

[TABLE]

The code also admits transversal implementations of two Clifford gates, namely $H\otimes H\cdot\mathrm{SWAP}$, where $H$ is the Hadamard gate, see Fig. 2.2a, and the controlled phase or C$Z$ gate, see Fig. 2.2b.

Moreover, if the five qubits have the right connectivity then there are fault-tolerant circuits preparing the logical states $\ket{00}_{\rm L}$, $\ket{0+}_{\rm L}$ and $\ket{00}_{\rm L}+\ket{11}_{\rm L}$. For the cat state $\ket{00}_{\rm L}$, see Equation (1), there exists fault-tolerant preparations including one ancillary qubit to verify the preparation. One post-selects on a successful preparation. The logical states $\ket{0+}_{\rm L}$ and $\ket{00}_{\rm L}+\ket{11}_{\rm L}$ are both two Bell pairs but with different pairings. They both also have fault-tolerant preparation circuits. In [8], some circuits are proposed, they can be adapted to the layout of the chip. We tested another preparation for $\ket{00}_{\mathrm{L}}$ inspired by [16], which is substantially shorter so more relevant to this layout.

The flagging technique in [16] for the preparation of $\ket{00}_{\rm L}$ can be implemented with the given CNOT connectivity, see Fig. 2.2a. We call this the fault-tolerant version one (FTv1). The technique based on a circular layout proposed by [8] cannot be implemented directly due to the connectivity. A clever introduction of one SWAP gate permits to implement it still fault-tolerantly at the cost of 8 CNOT gates in total, see Fig. 2.2b. We call this the fault-tolerant version two (FTv2). We present below, the results for FTv1, which is more appropriate for the layout. For both those circuits one can check that every possible single fault leads to a detectable error, or an error that stabilizes the prepared state. We also tried a non-fault-tolerant one that has the advantage of being short, involving only 3 CNOTs, see subsection 2.2. We call this the non-fault-tolerant version (NFT). For the preparation of $\ket{0+}_{\rm L}$, we want to create a Bell pair between $q_{1}$ and $q_{3}$ and between $q_{2}$ and $q_{4}$. There is a missing connection between $q_{1}$ and $q_{3}$, but we can do a similar SWAP trick, see the resulting circuit in Fig. 2.2a. This circuit is not fault-tolerant as an undetected logical $Z_{1}\otimes Z_{2}=Z\otimes\mathds{1}\otimes\mathds{1}\otimes Z$ can occur if the SWAP gate fails. This is the only possible harmful logical error for this circuit. We’ll see below that we only use this circuit in cases were the possible undetected $Z_{1}\otimes Z_{2}$ error doesn’t change the outcome of the sampling test. The preparation for $\ket{00}_{\rm L}+\ket{11}_{\rm L}$ can itself be straightforwardly implemented fault-tolerantly, see Fig. 2.2b. To summarize, our sets of initial states and gates are

[TABLE]

The $[[4,2,2]]$ code is only an error detecting code, that is, it can detect one Pauli error but cannot correct it. This means that in place of error correction we have to rely on post-selection to remove errors. In other words, we throw away runs where we detect that an error occurred, either from the ancilla measurement checking state preparation, or from the final measurement which indicates, when the parity of the outcomes is odd, that $S_{Z}$ has value $-1$.

As mentioned before, we cannot interleave rounds of error detection between state preparation and the gates. That means that the final circuit can only be tolerant to a single fault during the whole computation, except for the specific undetectable $Z_{1}\otimes Z_{2}$ failure mentioned above and when we use the non-fault-tolerant version to prepare $\ket{00}_{\mathrm{L}}$.

2.3 Comments on the tested circuits

Since we work with such a small system, we can exhaustively find and try all the logically equivalent circuits and optimize the bare version for each one. Essentially, we are making it most likely for the bare version of the task to prevail. From the set of states $S_{\rm FT}$, and the set of gates $G_{\rm FT}$, one can obtain 20 different stabilizer states. All the states with their most efficient bare preparation circuit, using the native set of gates provided by IBM, are listed in subsection 2.3. A brute force approach was used to find them.

Note that adding more gates in the sequence would test states that are already tested with shorter circuits. Therefore those would certainly give worse results as we cannot interleave error detections between gates. Hence we kept only these 20 different preparations. This still extensively probes the computational capabilities of the $[[4,2,2]]$ code.

3 Experimental results

The code and data can be found on GitHub [22]: it uses the Python SDK that can be found at [23].

3.1 Parameters and runs

Using the IBM chip one can run circuits in batches. For each individual run, 8192 shots are done right one after another in a short time, where each shot outputs 5 bits as measurement outcomes. We consider that the chip is exactly in the same conditions during each run. We consider all the runs to be independent of one another but each to be done in different conditions, so sampling from different output distributions.

For each run, IBM also provides calibration data describing the state of the chip such as: gate error rates, readout error rates, $T_{1}$, $T_{2}$ and fridge temperature. We give the average values that we observed for our runs in the appendix.

3.2 Performance metric

For each circuit run we want to compare the observed outcome distribution with the ideal one. The ideal distribution is 8192 independent samples from a distribution with four possible outcomes occurring with probabilities $p_{00}$, $p_{01}$, $p_{10}$ and $p_{11}$. The values for $p_{ij}$ can be read from subsection 2.3. Since we assume that the conditions stay identical during one run and that the 8192 shots are independent, we observe independent samples from a four-outcome distribution with some different probabilities $\tilde{p}_{00}$, $\tilde{p}_{01}$, $\tilde{p}_{10}$ and $\tilde{p}_{11}$.

We then use the statistical distance as a metric:

[TABLE]

This quantity is estimated for each run by

[TABLE]

where $n_{ij}$ is the number of observation of outcome $ij$ after post-selection and $n_{\rm valid}$ is the number of shots kept after post-selection. This estimator for $D$ is slightly biased except for the case where only one of the $p_{ij}$ is non-zero (because in this case it becomes linear). We use this estimator to keep the analysis simple.

Each of the runs has some different $\tilde{p}_{ij}$ and we have no information about how the $\tilde{p}_{ij}$s vary. Therefore we will assume that there are fluctuations around the mean of $\hat{D}$ following some unknown normal distribution and use this model to compute confidence intervals [24]. This means that the final data points and their confidence intervals don’t exactly reflect knowledge of $D$ but only of $\hat{D}$ which we believe is still a valid quantity to characterize the performance of the circuits.

3.3 Comparisons

We first need to decide on what pair of bare qubits is the best to be compared to the encoded qubits. It is not immediately clear how to choose this given only the calibration numbers. Thus we tried out the six different connected pairs and we found the performance shown in subsection 3.3. There is no clear “best pair” but one can see that the pairs $[2-0]$ or $[3-2]$ seem to be slightly better. Since we don’t have a systematic method for predicting the best pair given the calibration data and the circuit, we will look at average performance for each pair over all the circuits. When averaging, we find the pair $[2-0]$ to be the best, see subsection 3.3. The second observation that we can make based on subsection 3.3 is that the number of instructions does not explain the performance. It seems that the type of state sampled from is more important. Roughly it is easier to sample from equal superposition of the four computational basis states, than from equal superposition of two, than from just one. This can be understood with the fact that with more states in equal superposition there are less Pauli errors or readout errors that can affect the outcome distribution.

We then go on, comparing the encoded versions of the circuits to the elected best pair in subsection 3.3. The encoded circuits using the preparations $\ket{0+}_{\mathrm{L}}$ and $\ket{00}_{\mathrm{L}}+\ket{11}_{\mathrm{L}}$ are short and fault-tolerant and indeed show better performance than the bare ones. For the different preparations for $\ket{00}_{\mathrm{L}}$, the fault-tolerant version FTv1 is, except in a few cases, better than the non-fault-tolerant one despite being substantially longer. This shows that fault-tolerant design of circuits can be useful. Although they both compare unfavourably to the bare version, except for 4 circuits for FTv1 and only 1 circuit for NFT.

We cannot make an absolute statement as for some circuits the bare version is always better. We also don’t want to cherry pick the best version for each circuit since we don’t have a systematic way of predicting the best version. Average performance when fixing a preparation for $\ket{00}_{\mathrm{L}}$ are shown in subsection 3.3. One can see that FTv1, with $4.51\times 10^{-2}$, is better than the best bare implementation with $5.5\times 10^{-2}$, whereas NFT ($6.05\times 10^{-2}$) is worse.

4 Conclusion

In conclusion, we have shown that already on the IBM 5Q chip one can improve some quantum computation task, namely sampling from a class of states, by using error detection and fault-tolerant design of circuits. This improvement is only on average over 20 different states that the $[[4,2,2]]$ code can fault-tolerantly prepare. We also can see that shorter but non fault-tolerant circuits can be bested by longer but fault-tolerant circuits, showing the usefulness of these. As better and better hardware is developed, with more physical qubits, more connectivity and smaller error rates, demonstrations of fault-tolerance will become easier to produce and become more convincing. The set of gates shown to be fault-tolerant in this paper is very restricted. For the $[[4,2,2]]$ code a few more qubits and connections would be needed to realize fully fault-tolerant circuits with error detection in between logical units. Being able to demonstrate the fault-tolerance of larger gate sets, for example the whole Clifford group for several logical qubits would be an important milestone towards harnessing universal quantum computation.

Acknowledgements

I would like to thank the IBM Quantum Experience team for providing extensive access to the chip and support on how to interface with it. I also would like to thank Barbara Terhal for valuable comments and feedback. CV acknowledge support through the EU via the ERC GRANT EQEC and support by the Excellence Initiative of DFG. The views expressed are those of the author and do not reflect the official policy or position of IBM or the IBM Quantum Experience team.