Application of the Computer Capacity to the Analysis of Processors Evolution

TL;DR

This paper demonstrates how the concept of computer capacity can be used to predict future processor parameters by analyzing historical design changes, with a focus on Intel processors.

Contribution

It introduces a method to forecast processor parameters based on changes in computer capacity, aiding future processor design predictions.

Findings

Computer capacity varies with processor design parameters.

Predictions align with historical processor evolution.

Method applicable to different processor families.

Abstract

The notion of computer capacity was proposed in 2012, and this quantity has been estimated for computers of different kinds. In this paper we show that, when designing new processors, the manufacturers change the parameters that affect the computer capacity. This allows us to predict the values of parameters of future processors. As the main example we use Intel processors, due to the accessibility of detailed description of all their technical characteristics.

Tables

Table 1. Table 1: The summary of characteristics for selected processors

Processor	Pentium M	Intel	Ivy	Haswell	Skylake
		Core	Bridge
L1, KB	32	64	64	64	64
L2, KB	2048	6144	256	256	256
L3, MB	-	-	8	8	8
M, GB	1	16	16	16	16
$L{1}_{time}$, c.c.	3	3	4	4	4
$L{2}_{time}$, c.c.	10	15	12	12	12
$L{3}_{time}$, c.c.	-	-	30	36	42
$M_{time}$, c.c.	70	24	30	36	42
$R_i$	8	16	160	168	180
$R_v$	8	16	144	168	168
Computer	51.217	70.898	108.587	115.86	116.208
capacity,
bits/c.c.

Table 2. Table 2: Number of different instructions

number of operands	1	2	3
Pentium M (Dothan)	53	91	-
Intel Core (Wolfdale)	67	328	-
Ivy Bridge	21	99	10
Haswell	31	113	44
Skylake	35	134	48

Table 3. Table 3: Pentium M step 1

	0.5	2	5	10	20
$L1,L2,M,$
$L{1}_t,L{2}_t,M_t$	100	100	100	100	100
$R_i$	99.92	100.24	101.58	104.95	111.91
$R_v$	99.78	100.78	104.75	111.87	121.88
$R_i$ & $R_v$	99.72	101.03	105.97	113.95	124.39

Table 4. Table 6: Intel Core step 1

	0.5	2	5	10	20
$R_i$	99.73	100.79	104.36	110.67	119.84
$R_v$	97.48	105.81	118.08	128.87	140.01
$R_i$ & $R_v$	97.18	106.3	119	129.91	141.09

Table 5. Table 9: Ivy Bridge step 1

	0.5	2	5	10	20
$R_i$	99.96	100.17	101.16	103.66	108.57
$R_v$	89.3	111.16	126.05	137.35	148.66
$R_i$ & $R_v$	89	111.18	126.06	137.36	148.67

Table 6. Table 12: Haswell step 1

	0.5	2	5	10	20
$R_i$	99.71	101.85	110.89	120.75	131.04
$R_v$	91.57	110.03	123.66	134.01	144.37
$R_i$ & $R_v$	89.72	110.32	123.99	134.34	144.7

Table 7. Table 15: Skylake step 1

	0.5	2	5	10	20
$R_i$	99.66	102.08	111.51	121.41	131.67
$R_v$	91.83	109.95	123.53	133.85	144.17
$R_i$ & $R_v$	89.76	110.29	123.92	134.24	144.56

Table 8. Table 18: The values of Computer capacity and PassMark benchmark

Name	PassMark	Computer
		capacity, Mbit/s
Intel Pentium M	464	102434.84
Core 2 Duo T7300 (Intel Core)	1232	283593.72
Intel i5-3570 (Ivy Bridge)	6978	1610797.70
Intel Core i5-6600K (Skylake)	7884	1673398.77
Intel Xeon E5-2660v2 (Ivy Bridge)	13659	3179205.98
Intel Xeon E5-2640v3(Haswell)	14036	3151395.48

Equations

$$C(I)=\underset{T\to \infty }{\lim }\frac{\log N(T)}{T}.$$

$$Y^{-\tau (x_1)}+Y^{-\tau (x_2)}+\cdots +Y^{-\tau (x_n)}=1.$$

$$\frac{524014680}{X^1}+\frac{2448358122}{X^2}+\frac{81258594}{X^3}+\frac{4863059}{X^4}+\frac{19968745476}{X^5}+\frac{7936385025}{X^6}+$$

$$\frac{118510993664}{X^7}+\frac{4187392636}{X^8}+\frac{4198458}{X^9}+\frac{232644384}{X^{10}}+\frac{6978}{X^{11}}+\frac{14300162}{X^{12}}+$$

$$\frac{3440640}{X^{13}}+\frac{19117056}{X^{14}}+\frac{9516033}{X^{15}}+\frac{32768}{X^{16}}+\frac{79874982059}{X^{17}}+\frac{31745540097}{X^{18}}+$$

$$\frac{474046726144}{X^{19}}+\frac{16768421479}{X^{20}}+\frac{16678913}{X^{21}}+\frac{949315584}{X^{22}}+\frac{2778726}{X^{23}}+\frac{19267584}{X^{24}}+$$

$$\frac{13762561}{X^{25}}+\frac{39911425}{X^{26}}+\frac{131072}{X^{27}}+\frac{2752513}{X^{28}}+\frac{11010049}{X^{31}}+\frac{3145728}{X^{288}}+$$

$$\frac{9483265}{X^{34}}+\frac{11010048}{X^{35}}+\frac{168}{X^{36}}+\frac{5505024}{X^{38}}+\frac{11010048}{X^{40}}+\frac{1}{X^{41}}+\frac{6553}{X^{47}}+$$

$$\frac{3932160}{X^{50}}+\frac{9584997826560}{X^{51}}+\frac{3809464811520}{X^{52}}+\frac{56885276835840}{X^{53}}+$$

$$\frac{2009934594048}{X^{54}}+\frac{2001469442}{X^{55}}+\frac{111641886720}{X^{56}}+\frac{3145728}{X^{57}}+$$

$$\frac{2312110081}{X^{58}}+\frac{1651533582}{X^{59}}+\frac{4624220160}{X^{60}}+\frac{15728640}{X^{61}}+$$

$$\frac{1717986918}{X^{318}}+\frac{1321205760}{X^{65}}+\frac{1321205760}{X^{69}}+\frac{1}{X^{70}}+\frac{1}{X^{71}}+\frac{660602880}{X^{72}}+\frac{1321205760}{X^{74}}+$$

$$\frac{1}{X^{78}}+\frac{2147483648}{X^{80}}+\frac{5234686813011968}{X^{81}}+\frac{2080475715731456}{X^{82}}+$$

$$\frac{31066945855946752}{X^{83}}+\frac{1097692279629414}{X^{84}}+\frac{1093069176832}{X^{85}}+\frac{60971355734016}{X^{86}}+$$

$$\frac{1717986918}{X^{87}}+\frac{1262720385024}{X^{88}}+\frac{901943132160}{X^{89}}+\frac{2525440770048}{X^{90}}+$$

$$\frac{8589934592}{X^{91}}+\frac{3145728}{X^{93}}+\frac{8192}{X^{94}}+\frac{721554505728}{X^{95}}+\frac{721554505728}{X^{99}}+\frac{360777252864}{X^{102}}+$$

$$\frac{721554505728}{X^{104}}+\frac{32768}{X^{106}}+\frac{2}{X^{110}}+\frac{128}{X^{120}}+\frac{1717986918}{X^{123}}+\frac{512}{X^{132}}+\frac{128}{X^{134}}+$$

$$\frac{3932160}{X^{140}}+\frac{512}{X^{146}}+\frac{8192}{X^{151}}+\frac{32768}{X^{163}}+\frac{61440}{X^{166}}+\frac{2147483648}{X^{170}}+\frac{1}{X^{173}}+\frac{61440}{X^{180}}+$$

$$\frac{33554432}{X^{196}}+\frac{3932160}{X^{197}}+\frac{33554432}{X^{210}}+\frac{1}{X^{224}}+\frac{2147483648}{X^{227}}+\frac{6553}{X^{242}}+\frac{26214}{X^{254}}=1$$

Full text

Keywords: computer capacity, processors, evolution of computers, performance evaluation

11footnotetext: Institute of Computational Technologies of the Siberian Branch of the RAS, Novosibirsk State University22footnotetext: Siberian State University of Telecommunication and Information Sciences, Institute of Computational Technologies of the Siberian Branch of the RAS

This work was supported by Russian Foundation for Basic Research (grant 15-07-01851) and by Grant of Leading Scientific Schools (SS-7214.2016.9)

1 Introduction

A theoretical approach to estimating computer capacity was suggested in 2012 [1]. This approach uses only the description of the computer architecture investigated. The latter include the set of instructions, features of their execution, sizes of all the memory types, etc. Thus, no experiments with a working model of the computer are necessary. This method of estimating the computer capacity was used to evaluate the performance of a large number of different Intel and AMD processors [2]. In [2] we show that this characteristic is consistent with the values obtained empirically using benchmarks [3, 4, 5] (some of the results are presented in the appendix). This method was also used to estimate the performance of some supercomputers from TOP500 list [6].

In this paper we apply the method of estimating the computer capacity to study the evolution of processors. We assume that processor manufacturers are interested in changing those characteristics of processors that give the largest improvement in performance. Therefore, they need to be able to estimate the influence of changing some characteristic of a processor on its performance. At present, manufacturers use benchmarks to evaluate the performance, but this method is too complex and requires a working model of the computer investigated.Besides, benchmarks are inappropriate to use for the estimation of characteristics influence due to the necessity of building a working model of processor for each change.

Here we consider the evolution of Intel processors for the last 15 years. Each processor can be represented as a set of parameters and changing some of these parameters has a significant effect on its performance. Our investigation shows that in new processors the manufacturers usually increase the characteristics which affect the computer capacity the most. This, in turn, allows us to predict the direction of changes in the evolution of computers.

First, we note that there are clear tendencies that can be traced in the development of processors for the last 15 years. The first obvious tendency is the increase of the clock rate which causes the decrease of the task execution time. The second one is the widespread introduction of parallelism, in particular: by increasing the number of processors in computer; by increasing the number of computing cores in processor; by introducing threads and pipelines, etc. It is clear that the effect of these parameters is huge, but it is also obvious.

The emphasis in our work is on the quantitative estimation of the impact of the parameters whose role in the performance is not so obvious. These parameters include: sizes and access times to different kinds of memory (including registers, cache-memory etc.); the number of different instructions of certain type (instruction types are characterised by the number and kind of the operands).

For example, if we examine the Intel processor codenamed Wolfdale, we see that the increase of some parameters significantly affects performance, whereas changing the rest of the parameters has almost no effect. This, if we increase the size of level-1 cache memory in Wolfdale the value of the computer capacity almost does not change, but if the number of internal vector registers is increased, the growth of the computer capacity becomes perceptible. It turns out that in the processors of the succeeding microarchitectures (Sandy Bridge, Ivy Bridge etc.) these exact parameters were increased. This allows us to claim that using the suggested method may be useful for predicting which parameters will be changed in succeeding the future models.

2 Computer Capacity

All the theory behind the computer capacity and its estimation was described in details in the previous work [1], so here we only present the main definitions and a brief summary of the theory required in order to understand the results.

Let us consider a computer with the set of instructions $I$ and memory $M$. An instruction $x\in I$ is formed as the combination of its name and the values of its operands (two instructions with the same names and different values of operands are both included in $I$). For example, instructions mov eax, ebx and mov eax, ecx are different and included in $I$ independently. A computer task $X$ is a finite sequence of instructions $X=x_{1}x_{2}\dots,x_{i}\in I$. It is important to note that if there is a loop in a task which is repeated $m$ times, the body of this loop is included $m$ times in $X$. We denote $\tau(x)$ the execution time of instruction $x$. So the execution time of a computer task $X$ is given by $\tau(X)=\sum_{i=1}^{n}{\tau(x_{i})},\,X=x_{1}x_{2}\dots x_{n}$. Let consider the number of all possible computer tasks which execution times equal to $T$ as $N(T)=|\{X:\tau(X)=T\}|$.

Let, for example, there be a processor which has exactly $N(1)$ different tasks with execution times equal to 1 hour. In this case we can say that it can execute $N(1)^{2}$ different tasks in 2 hours because if instruction sequences $X_{1}$ and $X_{2}$ are 1-hour tasks, the combined sequence $X_{1}X_{2}$ is the 2-hour one (we did not take into account the 2-hour tasks with instruction starts at the end of the first hour and finishes and the beginning of the second, because the share of such sequences is negligible). In this way, the considered processor has $\approx N(1)^{k}$ tasks with execution times $k$ hours. So we can see that the number of possible tasks grows exponentially as a function of time ($N(T)\approx 2^{CT}$). Therefore, $C=\frac{\log{(N(T))}}{T}$ (or rather the limit of this value) is the adequate measure of the computer capacity. This limit is defined as follows:

[TABLE]

The main question here is how to estimate the value of $C(I)$ from (1). A direct calculation of the limit is impossible, but it is possible to calculate $C(I)$ with a method from combinatorial analysis. To do this, consider the set of instructions $I$ as an alphabet and assume that all words (sequences of instructions) over this alphabet are permitted (can be executed). This assumption allows us to estimate an upper-bound of the computer capacity, because for any processor the set of its permissible tasks is the subset of all possible tasks. Here, all execution times are integers (this statement is valid for most of the processors if the time unite is equal to the clock rate). A way to estimate the capacity was suggested by C. Shannon [7], who showed that the considered upper-bound of the capacity $C(I)$ is equal to the logarithm of the largest real solution $Y_{0}$ of the following characteristic equation:

[TABLE]

In [1] it was also shown that the computer capacity of a multi-core processing unit can be defined as the sum of capacities of the cores.

3 The computer capacity of Intel processors

The present work is based on the analysis of Intel processors produced over the last 15 years, because the information about these processors architectures (with the full description of instruction set) is public and easily accessible. In our previous works we have shown that the computer capacity correlates well with the values of benchmarks [8, 5] and can be used as a measure of computer performance [2].

We have identified a list of processors to analyze: Pentium M (Dothan processor), Intel Core (Wolfdale), Ivy Bridge, Haswell and Skylake. In this paper we analyze these processors in details, evaluate their computer capacity values and perform some investigations about the effect of parameters on performance. Pentium M and Wolfdale architecture differs strongly from Ivy Bridge, Haswell and Skylake, so the comparison of this architectures would be quite interesting. Skylake is considered here because it is the latest Intel microarchitecture with a detailed description published (at the time of the preparation of this paper). Here, we present the details of the calculation of the computer capacity for Intel Pentium M, Core, Ivy Bridge, Haswell and Skylake microarchitectures. The structures of the described processors pipelines are similar to each other, and the features of building the equation (2) for that structure are presented in [red12_1, 2].

In table 1 we present the summary of technical characteristics and the values of the computer capacity for all the processors chosen. The following notation is used: L1,L2,L3 is the size of level-1, level-2 and level-3 caches, M is the size of RAM, $L1_{t},L2_{t},L3_{t},M_{t}$ is the memory latencies for level-1, -2, -3 and RAM respectively, c.c. stands for clock cycles, $R_{i}$ is the number of integer registers, $R_{v}$ is the number of vector (floating point) registers. The detailed description and the lists of instructions of the described microarchitectures are presented in [9]. The characteristic equations of all the processors described and all the tools for evaluation of the computer capacity can be found in [10].

4 Analysis of Intel processors evolution

To analyze the evolution of Intel processors we divide them into 5 groups: (Pentium M, Intel Core), (Intel Core, Ivy Bridge), (Ivy Bridge, Haswell), (Haswell, Skylake) and (Skylake and the prediction for its successor). The investigated characteristics are the following:

• •

Physical characteristics of processor: the size of all memory types; the access time of all memory types; the number of different registers. Here, the memory types are the 1-level cache, the 2-level cache, the 3-level cache (if processor contains this level) and the main memory (RAM). Registers are also of two types: integer and vector.

• •

The instruction set is another characteristic that affects the performance. It can be observed that the instruction set changes from one processor to another. Here, we isolate the fastest instructions from instruction set of each examined processor, and calculate their number. The fastest instruction is the one whose execution time equals 1 and does not have memory cells in the list of operands (access to the memory cell greatly increases the execution time of an instruction). We group all these instructions by the number of operands and present the results in table 2 (the names of columns signify the number of operands in the investigated instructions: the number of instructions with single operand (second column), with two operands and with three operands). In most cases, these operands are registers of different types.

We examined the influence of changing the value of a single characteristic (from the physical group) and identified those of them which have a nonzero influence on the value of the computer capacity. We also examined all the possible pairs of different characteristics, but only one pair ($R_{i}$,$R_{v}$) was included because all other pairs either have no effect on the value of the computer capacity or their effect equals the effect of a single characteristic. The values were calculated at $\times 0.5,\times 2,\times 5,\times 10,\times 20$ of the original value.

Next we try to add instructions in the instruction set and to show the influence of this addition on the value of the computer capacity. The number of instructions in the modified instruction set is obtained as the original value $\times 1.1,\times 1.25,\times 1.5,\times 2$. The last step is the combination of the two previous steps. Here, we want to show the influence of increasing the number of registers and adding instructions of a new type simultaneously. It is shown above that in the Ivy Bridge processors a new type of instructions appeared: instructions with three register operands, and at the same time the number of registers is increased almost 10 times in relation to Intel Core (Wolfdale) processors. So, in this part we add the instructions of a new type: for Pentium M and Intel Core we add instructions with 3 operands, for the remaining processors we add instructions with four operands. In the experiments we add 8, 16, 32 and 64 instructions. Increasing the number of registers is performed in the following way: $\times 2,\times 5,\times 10$ of the original value. Following is the list of added instructions types in the second and third steps:

cmd r 1 / cmd x 1 - the instruction with the name ”cmd”, with a single integer register operand (r) or vector register (x) and with the execution time equals to 1; 2. 2.

cmd r,r 1 / cmd x,x 1- the instruction with two integer or two vector register operands; 3. 3.

cmd r,r,r 1 / cmd x,x,x 1 - the instruction with three integer or three vector register operands, codenamed cmd1 and cmd2 respectively in the last step. 4. 4.

cmd r,r,r,r 1 / cmd x,x,x,x 1 - the instruction with four integer or four vector register operands, codenamed cmd3 and cmd4 respectively in the last step.

All the results in the tables are presented in percent relative to the original value of the computer capacity. The characteristics with the same results are merged into a single row.

4.1 Pentium M and Intel Core

The results of the analysis of Pentium M are presented in Tables 5,5 and 5, one for each step of investigation. The first row is filled with 100 and it means that the characteristics from this row have no influence on the computer capacity. So the role of the size and the access time of cache-memory and RAM are insignificant for the computer capacity. In the following subsections we exclude from the tables those characteristics that do not affect the value of computer capacity. We can also observe that the increase in the number of instructions has no significant effect (for the instructions of existing types). However, there are some characteristics which change the value of the computer capacity by more than 1%. Obviously, to increase the capacity, we need to increase the number of registers (integer or vector) and add some instructions of a new type. As we can see in Tables 1 and 2, the number of registers was doubled in Intel Core, the size of memory of different kinds was also increased, but the access times are almost unchanged. Increase in the Intel Core computer capacity is also explained by the improvement of the throughput of its pipeline (it grew from 3 $\mu$ops per cycle to 4).

4.2 Intel Core and Ivy Bridge

In tables 8,8 and 8 the results are close to those for the previous processor, except for the effect of adding the instructions with 2 operands. We noted that the 10-20 fold increase of the number of registers and adding the instructions with three operands gives the best effect on the value of computer capacity. Indeed, the manufacturer change exactly this characteristics in the succeeding processor. In Ivy bridge the number of integer and vector registers increased tenfold and 10 fast instructions with 3 register operands were added.

4.3 Ivy Bridge and Haswell

The results for Ivy Bridge analysis are presented in tables 11, 11 and 11. Here, we observe tendencies similar to those in the previous processors. It is interesting to observe that starting from Ivy Bridge the characteristics related to cache-memory and RAM are almost unchanged. We can also notice that starting with Ivy Bridge the effect of the number of commands with one register becomes insignificant and we exclude them from the tables of the following subsections.

4.4 Haswell and Skylake

Haswell processors (tables 14,14 and 14) were improved by increasing the number of registers and by adding some instructions of the existing types. We can observe that most of investigated characteristics are unchanged for Ivy Bridge, Haswell and Skylake. The main tendencies are for increasing the number of registers (but not as much as for Intel Core), changing the instruction set and making some improvements to the processor pipeline.

4.5 Skylake and the prediction of its successor

The results obtained for this last processor from our list (tables 17,17 and 17) present the direction for making predictions for succeeding processors. We can note that as far as the characteristics from the technical group are concerned, the biggest effect on the computer capacity is reached by increasing the number of vector registers. To achieve the effect close to the Intel Core – Ivy Bridge capacity increase we need to increase tenfold the number of registers and to add a large number of new fast instructions with four registers.

The first step of our research shows that some parameters do not affect the performance starting from the first examined processor. These parameters are sizes of all types of memory and theirs latencies. Certainly, we do not want to claim that these parameters are useless and can be freely removed, but in the previous models the level of saturation was reached for these parameters, so increasing them more is inefficient. Also we isolate the parameters which have a significant influence on the value of computer capacity and that have been changed substantially during the evolution process. In fact, the registers of a processor is the fastest memory (they can be accessed nearly instantly), so it is expected that this value has the highest influence among all the presented parameters. Nevertheless, it is important to note that the really significant effect on the value of computer capacity (more than 10%) is obtained at 10-20 fold increase.

The second step of research shows the influence of the instruction set on the performance of processors. All the obtained results show the growth of the computer capacity in the range of 1-2% even with a double increase of the number of fastest instructions. Considering the complexity of designing new instructions, we can speak of the saturation of the instruction set with the existing types of instructions. It is also clearly seen that this exact way has been chosen by the manufacturers of the processors. Starting from Ivy Bridge processor a new type of fast instructions with three register operands was added. This statement is proved by the results from the third step of research where we simultaneously increase the number of registers and add instructions with three operands. As we can see in Table 2, 10 instructions with three register operands were added, and in Table 1 we see that the number of integer registers increased from 16 to 160 (10 times). The corresponding predicted value in Table 8 is 147.49%, which is close to the original values of computer capacity for processors Intel Core and Ivy Bridge from table 1, which is 153.16%.

5 Conclusions

After presenting all the obtained results we can make some conclusions. The last considered microarchitecture is Skylake (Kaby lake is just its modification) and its successor Cannon Lake, whose characteristics we try to predict, is not released yet. The investigations show that just a small set of Skylake parameters affects the computer capacity. In order to achieve greater performance the manufacturer needs to increase the number of registers (as we can see in table 17, vector registers have a stronger effect on the computer capacity value then integer registers) and add some new processor instructions. On the other hand, it is clearly seen that it makes no sense to change the values of RAM and cache-memory sizes or access times. In the context of presented work we do not consider the other parameters whose influence is obvious and linear (the number of cores, the clock rate etc.). So, we can predict that in Cannon Lake the manufacturer will increase the number of registers and add some new vector instructions with three or more operands.

We can see that a direct application of computer capacity gives a new approach to analyse computer performance. Generally speaking, all changes are aimed at increasing computing capacity, defined in (1) (and estimated based on the equation (2) ) In this paper we successfully applied the computer capacity for investigation and prediction of processor evolution.

APPENDIX

In table 18 we present the values of Computer Capacity and PassMark benchmark for all processor microarchitectures investigated in paper. Here, the processor Ivy Bridge was presented twice just to show how Computer Capacity would behave with different numbers of cores (i5-3579 has 4 cores and E5-2660v2 has 10 cores). At figure 1 we can see the results of comparison these values. As the measurement units are different we took the value of the first processor in list (Intel Pentium M) as 1 and build the graph in relation to the values of this processor. For example, we divide the value of Computer Capacity for i5-6600K (1673398.77) by 102434.84 and get the result 16.336, and analogously we divide the value of PassMark benchmark (7884) by 464 and get 16.991.

APPENDIX 2

The characteristic equation (2) for Haswell processor:

[TABLE]