Cache Hierarchy Optimization

TL;DR

This paper presents an analytical framework for optimizing cache hierarchy and area allocation in Chip Multiprocessors, considering power, bandwidth, and resource constraints, with extensions for data sharing effects.

Contribution

It introduces a closed-form analytical solution for cache hierarchy optimization and incorporates data sharing impact into the model.

Findings

Analytical model for cache access time validated with CACTI simulations.

Optimized cache hierarchy improves resource utilization and scalability.

Incorporating data sharing reduces cache miss rates.

Abstract

Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.