A self-aligned nano-fabrication process for vertical NbN-MgO-NbN Josephson junctions

TL;DR

This paper introduces a novel self-aligned fabrication process for vertical NbN-MgO-NbN Josephson junctions, enabling scalable, high-performance superconducting circuits with customizable impedance.

Contribution

It presents a new self-aligned process for fabricating vertical NbN-MgO-NbN Josephson junctions with a wide range of sizes and impedance options, suitable for complex microwave circuits.

Findings

Junctions have high gap voltages (> 4 mV)

Low sub-gap leakage currents observed

Process supports a broad range of junction areas

Abstract

We present a new process for fabricating vertical NbN-MgO-NbN Josephson junctions using self-aligned silicon nitride spacers. It allows for a wide range of junction areas from 0.02 um^2 to several 100 um^2. At the same time, it is suited for the implementation of complex microwave circuits with transmission line impedances ranging from < 1 Ohm to > 1 kOhm. The constituent thin films and the finished junctions are characterized. The latter are shown to have high gap voltages (> 4 mV) and low sub-gap leakage currents.

Figures

Tables

Table 1. Table 1: Procedure of etching the trilayer and counter electrode. Thin lower layers (below approximately 30   nm times 30 nanometer 30\text{\,}\mathrm{nm} ) are transparent and allow for end point detection in the first step. If thicker lower layers are required, the first etch has to be timed instead. For the final etch of the counter electrode (and upper part of the trilayer, see paper) the etch is stopped before the MgO step.

		CH2F2 ($\mathrm{SCCM}$)	SF6 ($\mathrm{SCCM}$)	Ar ($\mathrm{SCCM}$)	Pressure ($\mathrm{mTorr}$)	ICP ($W$)	Forward ($W$)	Time ($s$)
upper NbN		25	5	40	5(15)	500	70	EPD
NbN landing		10	10	40	20	500	20	15
	MgO			100	5	500	150	20
$4\times$	Pump				0			150
	Vent				atmospheric pressure			90
lower NbN		25	5	40	5(15)	500	70	EPD
NbN landing		10	10	40	20	500	20	15

Table 2. Table 2: Procedure for etching Si 3 N 4 dielectric. Before this etch the MgO cap layer is removed by dipping the wafer in 1 % acetic acid for 20   s times 20 second 20\text{\,}\mathrm{s} .

	CH2F2 ($\mathrm{SCCM}$)	SF6 ($\mathrm{SCCM}$)	Ar ($\mathrm{SCCM}$)	Pressure ($\mathrm{mTorr}$)	ICP ($W$)	Forward ($W$)	Time ($s$)
Si3N4	25	5	40	5(15)	(1000,500),250	(150),50	EPD

Table 3. Table 3: Etch for removing resist residues after etching and stripping.

	O2 ($\mathrm{SCCM}$)	Pressure ($\mathrm{mTorr}$)	ICP ($W$)	Forward ($W$)	Time ($s$)
O2 plasma	45	30	500	0	300

Full text

††preprint: AIP/123-QED

I Introduction

Josephson junctions (JJ) are the key nonlinear element used in superconducting circuitsTaylor et al. (1967); Devoret and Schoelkopf (2013); Clarke and Braginski (2004). In applications where large critical currents are needed, typically Nb–Al2O3–Nb, NbN–MgO–NbN or NbN–TaN–NbN junctions are used. This is the case for superconducting quantum interference device (SQUID) magnetometersClarke and Braginski (2004), Josephson mixersTucker and Feldman (1985) or rapid single flux quantum (RSFQ) logic circuitsLikharev and Semenov (1991). The high critical temperature and large superconducting gap of Nb and NbN enable these devices to operate at liquid helium temperatures ($4\text{\,}\mathrm{K}$) and up to very high frequencies (above $1\text{\,}\mathrm{THz}$ for NbN). Such junctions are typically fabricated by first depositing the junction stack and then etching a pillar from it. The main difficulty is to contact the top of this pillar without short-circuiting it to the bottom layer. Common solutions to this problem, such as an additional insulating layer that is etched away above the pillar or anodic oxidation of Nb usually limit the minimum junction area to approximately $1\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$ Nakamura et al. (2011); Hyp (2012, 2015); Kiviranta et al. (2016). This results in high critical currents and large shunting capacitances.

However, certain superconducting quantum circuits, such as Josephson qubits and Josephson photonic devices, require these quantities to be small. Because of this, it is much more common to use Al–Al2O3–Al junctions, which can be fabricated using shadow angle evaporation; a technique allowing for very small Josephson junction sizes down to $0.01\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$ or less Dolan (1977); Lecocq et al. (2011). The downside of this approach is that the low gap of Aluminum sets an ultimate limit for the fabricated devices in operation frequency (below $100\text{\,}\mathrm{GHz}$) as well as temperature.

Here, we report on a fabrication process able to simultaneously obtain NbN–MgO–NbN junctions with surface areas as small as $0.02\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$ and as large as several $100\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$. This marks an important step towards bringing the advantages of NbN–MgO–NbN junctions to quantum circuits that were so far limited to Al junctions and opens the possibility for such circuits to operate at much higher frequencies. It is particularly useful for the field of Josephson photonicsHofheinz et al. (2011); Gramich et al. (2013); Armour, Kubala, and Ankerhold (2015); Leppäkangas et al. (2015); Grimm (2015), which requires small junctions and could provide devices like quantum microwave sources and amplifiers able to function up to the gap frequency of the superconductor.

The presented NbN junction fabrication process also enables us to implement very versatile passive microwave circuits at no extra cost. The large kinetic inductance of NbN can be used to design high impedance circuit elements, which are useful for many quantum circuits in general and Josephson photonics in particular.

II Fabrication of Josephson junctions

The NbN thin films are prepared by DC magnetron sputtering on Si($500\text{\,}\mathrm{\SIUnitSymbolMicro m}$):$\textrm{SiO}_{2}$($500\text{\,}\mathrm{nm}$) substrates. After cleaning the wafers by back-sputtering in the deposition chamber, a $20\text{\,}\mathrm{nm}$ magnesium oxide (MgO) buffer layer is added as etch stop and to improve the superconducting properties of the NbN film. This is followed by the deposition of an NbN($10\text{\,}\mathrm{nm}$):MgO($4\text{\,}\mathrm{nm}$):NbN($190\text{\,}\mathrm{nm}$) stack (hereafter called the trilayer) Larrey et al. (1999). The NbN is DC magnetron sputtered from an Nb target in an atmosphere of Ar and N2 (see supplementary information for detailed process parameters). Scanning electron microscope images of cuts through the produced NbN films show them to be columnar with an average column diameter of $\approx$20\text{,}\mathrm{nm}$$.

The aspect ratio imposed by the thickness of the deposited layers and the lateral junction sizes calls for very directional etch processes. We have developed several dry etch recipes on an Oxford ICP Plasmalab100 reactive ion etcher. During the etch, NbN is attacked both chemically, with $\textrm{SF}_{6}$, as well as mechanically with Ar. A moderate platen power generates an auto-polarization voltage of $\approx$190\text{,}\mathrm{V}$$ accelerating the ions towards the sample and makes the etch more directional. Moreover, $\textrm{CH}_{2}\textrm{F}_{2}$ is added to the mixture, with the effect of polymerizing the exposed surface of the NbN film, making it less sensitive to the chemical etch. While in the vertical direction the Ar bombardment constantly ablates the polymer film and leaves the surface exposed to the chemical etch, the sidewalls of steps and trenches stay protected, preventing any underetch and assure smooth and steep sidewalls (see Fig. 1).

The MgO-barrier is etched purely mechanically with an argon plasma. MgO is insensitive to the NbN etch described above, allowing us to use the buffer and barrier layers as effective etch stops, despite their very small thickness. Consequently the NbN etch can run longer to counteract inhomogeneities in deposition and etching rate across the wafer.

During the entire fabrication process described below optical lithography (OL) and electron beam lithography (EBL) steps are combined in order to be able to define small structures with high precision, while keeping the processing times for bigger structures such as coplanar waveguide (CPW) transmission lines Pozar (2011) low. The following description will, however, focus on the elaboration of a single small Josephson junction and thus disregards some of the OL steps.

To begin with, a step is etched into the trilayer using an EBL defined Ti($10\text{\,}\mathrm{nm}$):Pt($60\text{\,}\mathrm{nm}$) hard-mask (Fig. 1), which is subsequently removed with an Ar plasma. Next, the entire wafer is coated with a $300\text{\,}\mathrm{nm}$ thick film of $\textrm{Si}_{3}\textrm{N}_{4}$ by chemical vapor deposition. A $10\text{\,}\mathrm{nm}$ thick layer of MgO is deposited on top of the SiN in order to protect it from overetching during some of the following fabrication steps. An optical lithography step is carried out defining regions where the dielectric will be etched. The entire junction lies in such an area. First, the MgO in these areas is removed by a dip in 1 % acetic acid. We then perform a directional dry-etch of the SiN, similar to the one developed for NbN. The vertical thickness of the dielectric at the step is considerably bigger than elsewhere. Hence, it can be etched away on all flat surfaces while leaving behind a self-aligned spacer protecting the side of the trilayer (Fig. 1).

Finally, after a back-sputtering step, the NbN counter-electrode ($\approx$350\text{,}\mathrm{nm}$$) is deposited. Another EBL defined hard-mask protects an area in the shape of a finger overlapping with the step. Once the unprotected areas are etched down all the way to the MgO tunneling barrier, this finger forms the vertical Josephson junction shown in Fig. 1 (see supplementary material for details of the etch recipes).

III Simultaneous implementation of passive elements

The fabrication steps used to implement the junction enable us to simultaneously fabricate very versatile passive microwave circuits on the same chip. In particular, the process allows for various types of transmission lines: A line defined in the counter-electrode layer on top of the SiN forms a microstrip line together with the ground plane given by the trilayer. This case is ideal for low-impedance transmission lines (we estimate $65\text{\,}\mathrm{\SIUnitSymbolOhm}$ for $1\text{\,}\mathrm{\SIUnitSymbolMicro m}$ wide lines, down to $<$1\text{,}\mathrm{\SIUnitSymbolOhm}$$ for $100\text{\,}\mathrm{\SIUnitSymbolMicro m}$ wide lines. However, these impedances depend critically on the exact dielectric thickness and, because of high kinetic inductance fractions around 0.8, on the NbN material properties. Coplanar wave guide (CPW) geometries using the full thickness of the trilayer can be tuned for transmission line impedances between $20\text{\,}\mathrm{\SIUnitSymbolOhm}$ and $150\text{\,}\mathrm{\SIUnitSymbolOhm}$ Grimm (2015). This impedance and propagation speed are accurately controlled by lateral geometry because kinetic inductance fractions are low ($<0.25$ except for extreme geometries) and the substrate dielectric constant is well known. For even higher impedances, the dielectric on top of the CPW center conductor can be removed before the counter-electrode etch step. As a result, the upper part of the trilayer is etched away during this step, thinning down the center conductor to $10\text{\,}\mathrm{nm}$ like in the junction area (see Fig. 1). For such thin layers the NbN kinetic inductance is dominating and leads to characteristic impedances of up to $3.5\text{\,}\mathrm{k\SIUnitSymbolOhm}$ for a $1\text{\,}\mathrm{\SIUnitSymbolMicro m}$ wide wire. In areas where the SiN dielectric layer is not etched, it separates the trilayer and the counter-electrode, allowing for straightforward implementation of parallel plate capacitors. Where needed, holes can be etched in the dielectric to provide vias connecting the two layers. This enables us to fabricate crossovers between the ground planes of the CPW transmission lines, thus effectively eliminating parasitic modes Abuwasib, Krantz, and Delsing (2013); Chen et al. (2014); Kwon et al. (2001); Koster et al. (1989).

IV Properties of the fabricated films and junctions

Temperature dependent resistance measurements of the deposited layers were performed in a commercial physical property measurement system (PPMS) (see Fig. 2).

We calculate the value of the kinetic inductance $L_{\mathrm{kin},\square}$ from the square resistances $R_{\square}$ (taken at $20\text{\,}\mathrm{K}$) of the film, its thickness $d$ and the superconducting gap $\Delta$ estimated from the critical temperature, according to Kautz (1978); Van Duzer and Turner (1981) $L_{\mathrm{kin},\square}=\mu_{0}\lambda\text{coth}\left(d/\lambda\right)$. Here $\lambda=(\hbar R_{\square}d/(\mu_{0}\pi\Delta))^{1/2}$ is the London penetration depth of a local superconductor in the low temperature limit $k_{\textrm{B}}T\ll\Delta$Barends (2009); Mattis and Bardeen (1958). For the bottom layer $d\ll\lambda$ so that $L_{\mathrm{kin},\square}\approx\hbar R_{\square}/(\pi\Delta)$ can be estimated without knowing the exact film thickness.

A typical current-voltage characteristic of a superconducting interference device (SQUID) consisting of two parallel junctions with a total area of $0.04\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$ (squares of $150\text{\,}\mathrm{nm}$ side-length) measured at $4.2\text{\,}\mathrm{K}$ is shown in Fig. 3. The gap voltage $V_{\mathrm{gap}}$ can be defined as the voltage at the steepest part of the curve, where $\textrm{d}I/\textrm{d}V$ is maximized Kawakami, Wang, and Miki (2001). Here, $V_{\mathrm{gap}}=$4.15\text{,}\mathrm{mV} corresponding to an emission frequency of $\approx$1\text{\,}\mathrm{THz} in the framework of Josephson photonics Hofheinz et al. (2011); Ingold and Nazarov (2005); Grimm (2015). A normal state resistance $R_{\mathrm{N}}\approx$1.5\text{,}\mathrm{M\SIUnitSymbolOhm} can be extracted from the same curve far above $V_{\mathrm{gap}}$ at $7\text{\,}\mathrm{mV}$. Together with the Ambegaokar-Baratoff formula at zero temperatureTinkham ([2004](#bib.bib29)) $I_{\mathrm{c}}R_{\mathrm{N}}=\pi\Delta(0)/2e$ and the relation $2\Delta=eV_{\mathrm{gap}}$ we can evaluate the theoretical critical current at zero temperature to be $\approx$2.2\text{\,}\mathrm{nA}. The critical current density is $\approx$5.5\text{,}\mathrm{A}\text{,}{\mathrm{cm}}^{-2}. Note that, even though our junctions are optimized for low critical current densities, $J_{\mathrm{c}}$ can easily be increased by several orders of magnitude with this deposition process Larrey *et al.* ([1999](#bib.bib17)). The current branch of the IV in Fig. [3](#S4.F3) is not visible, because the associated energy scaleTinkham ([2004](#bib.bib29)) $E_{\mathrm{J}}=\Phi_{0}I_{\mathrm{c}}/(2\pi)\approx$4.5\text{\,}\mathrm{\SIUnitSymbolMicro eV}, where $\Phi_{0}$ is the magnetic flux quantum, is much smaller than the thermal energy at $4.2\text{\,}\mathrm{K}$ ($k_{\mathrm{B}}T\approx$360\text{,}\mathrm{\SIUnitSymbolMicro eV}$$). The ”knee” in the current-voltage characteristic is usually associated with the formation of a thin normal metal layer close to the junction barrier and has frequently been observed in NbN–MgO–NbN Josephson junctionsShoji et al. (1987); Shoji (1991); Longobardi et al. (2011).

In the context of this work we took particular interest in minimizing the leakage current under the gap Grimm (2015). In order to quantify the subgap leakage we compare the resistance under the gap ($R_{\mathrm{S}}$) at $3\text{\,}\mathrm{mV}$ to $R_{\mathrm{N}}$. A linear fit of the current voltage characteristic in Fig 3 between $-3\text{\,}\mathrm{mV}$ and $3\text{\,}\mathrm{mV}$ gives $R_{\mathrm{S}}\approx$80\text{,}\mathrm{M\SIUnitSymbolOhm}$$ leading to $R_{\mathrm{N}}/R_{\mathrm{S}}<0.02$. While the measured gap voltage on this specific sample is lower than the best values reported in the literature, the subgap resistance is comparable to the numbers achieved in other groups Kawakami, Wang, and Miki (2001); Longobardi et al. (2011); Shoji et al. (1985). In particular, it should be pointed out that the smallest NbN–MgO–NbN tunnel junctions found in the literature have surface areas around $0.1\text{\,}{\mathrm{\SIUnitSymbolMicro m}}^{2}$, several times bigger than the junction presented here, while showing considerably more subgap leakageKawakami, Wang, and Miki (2001); Hunt et al. (1989); LeDuc et al. (1991).

V Possible variations

The current process is not suitable for applications requiring resonators with very high quality factors, such as circuit QED. CPW resonators realized with this processGrimm (2015) typically have intrinsic quality factors of $10^{4}$. We attribute this low value to dielectric loss in the MgO and $\textrm{SiO}_{2}$ buffer layers. We expect a significant increase of this value by omitting the MgO buffer layers and using sapphire substrates instead. The latter allow to directly grow high quality NbN films without buffer layer and provide a good etch stop. If transmission lines with higher impedances are needed, the thickness of the lower NbN layer can be reduced. Replacing the silicon substrate with a silica substrate, increases the characteristic impedances of CPWs by another factor $\sim 1.7$.

If high kinetic inductance is not desired, the process, with slight adjustments, should be applicable also to Nb-(Al)-Al2O3-Nb trilayers, where the barrier is formed by oxidizing a thin proximized aluminum layer. We expect that such a process yields lower leakage current below the gap because of the more uniform self-passivating barrier.

The current density is voluntarily kept low for the application in mind Grimm (2015), but can be increased by several orders of magnitude by decreasing the thickness of the MgO barrier layer Larrey et al. (1999).

Finally, if only larger junction sizes are needed, the junctions can exclusively be defined by optical lithography, considerably reducing fabrication times. In this case, the geometry is changed so that a counter-electrode wire crosses a trilayer wire. This makes the junction size insensitive to slight misalignments between the two optical lithography steps.

VI Conclusion

In conclusion, we have developed a new fabrication process for vertical NbN–MgO–NbN Josephson with self-aligned SiN spacers allowing for very small junction areas. The measured junction current–voltage characteristics show a high gap voltage and to our knowledge the lowest subgap leakage current at these junction sizes reported so far. The process allows for simultaneous fabrication of very large Josephson junctions and extremely versatile passive microwave circuits with characteristic impedances ranging from $<$1\text{,}\mathrm{\SIUnitSymbolOhm} to $>$1\text{\,}\mathrm{k\SIUnitSymbolOhm} .

Acknowledgements.

We acknowledge financial support from the Grenoble Nanosciences Foundation grant JoQOLaT, from French National Research Agency / grant ANR14-CE26-0007 - WASI, and from the European Research Council under the European Unions Seventh Framework Programme (FP7/2007-2013) / ERC Grant agreement No 278203 WiQOJo, as well as fruitful discussions with the Plateforme Technologique Amont (PTA) cleanroom team, François Lefloch and Jean-Claude Villegier.

Supplementary material: Detailed process parameters

VI.1 Film deposition

NbN and MgO films are deposited in an Alcatel SCM600 sputter tool. The NbN–MgO–NbN trilayer is deposited in situ without exposing the sample to air between steps. Substrates are not actively heated, but their temperature increases above ambient temperature during the process.

NbN films prepared by reactive DC magnetron sputtered from a $150\text{\,}\mathrm{mm}$ Niobium target at $4\text{\,}\mathrm{A}$ and $\approx$400\text{,}\mathrm{V} in an atmosphere of $1.5\text{\,}\mathrm{Pa}$ of Ar and $0.2\text{\,}\mathrm{Pa}$ of N2. The latter partially nitrates the target surface after the target surface has been conditioned in an atmosphere containing more nitrogen. The deposition rate is $\approx$3.3\text{\,}\mathrm{nm}\text{\,}{\mathrm{s}}^{-1}. For very thin layers we rotate the sample stage over different targets at $\approx$0.6\text{,}\mathrm{Hz}$$ reducing the average deposition rate by approximately a factor 7 for a more precise control of thickness.

The MgO barrier is RF magnetron sputtered at $450\text{\,}\mathrm{W}$ in an Ar atmosphere at $1.3\text{\,}\mathrm{Pa}$ for $100\text{\,}\mathrm{s}$, in the same chamber as the NbN films, also with rotating sample. For deposition of the buffer layer we increase power to $550\text{\,}\mathrm{W}$, keep the sample on top of the target and use an atmosphere of $1.25\text{\,}\mathrm{Pa}$ of Ar and $0.1\text{\,}\mathrm{Pa}$ of N2.

SI3N4 is deposited in a Corial D250L plasma enhanced chemical vapor deposition (PECVD) tool at $280\text{\,}\mathrm{\SIUnitSymbolCelsius}$ and $200\text{\,}\mathrm{W}$ at a pressure of $200\text{\,}\mathrm{Pa}$ with flows of $100\text{\,}\mathrm{SCCM}$ of SiH4, $500\text{\,}\mathrm{SCCM}$ of NH3 and $100\text{\,}\mathrm{SCCM}$ of Ar.

VI.2 Etch parameters

Tables 1, 2, 3 give details on our etch recipes in an Oxford Plasmalab 100 ICP etcher. The different rows of each table correspond to the steps followed chronologically during the procedure. Landing steps are performed to homogenize the NbN etch over the entire wafer and are possible because MgO provides a very good etch stop. Values in parentheses are used to start the plasma and then quickly ramped down to the regular parameters. The purely mechanical MgO etch steps are interleaved with pumping and venting of the process chamber in order to evacuate excess material. EPD stand for “end point detection”, which is performed using in situ laser reflectometry.