# Characterisation of novel prototypes of monolithic HV-CMOS pixel   detectors for high energy physics experiments

**Authors:** Stefano Terzo (1), Emanuele Cavallaro (1), Raimon Casanova (1),, Francesco Di Bello (2), Fabian F\"orster (1), Sebastian Grinstein (1, 3),, Ivan Per\'ic (4), Carles Puigdengoles (1), Branislav Ristic (2, 5), Mateus, Vicente Barrero Pinto (2), Eva Vilella (6) ((1) Institut de F\'isica, d'Altes Energies, Barcelona, Spain, (2) D\'epartement de Physique Nucl\'eaire, et Corpusculaire, University of Geneva, Geneva, Switzerland, (3) Instituci\'o, Catalana de Recerca i Estudis Avan\c{c}ats, Barcelona, Spain, (4) Karlsruher, Institut f\"ur Technologie, Karlsruhe, Germany, (5) CERN, (6) University of, Liverpool, Liverpool, United Kingdom)

arXiv: 1705.05146 · 2017-06-28

## TL;DR

This paper presents the development and initial testing of novel monolithic HV-CMOS pixel detectors for high energy physics, aiming to improve cost, material budget, and radiation hardness for future collider experiments.

## Contribution

It introduces the H35DEMO HV-CMOS demonstrator chip with monolithic pixel matrices and reports initial beam test results demonstrating its potential for high energy physics applications.

## Key findings

- Successful characterization of H35DEMO chips.
- First beam test results with high energetic pions at CERN SPS.
- Evidence of charge drift in depleted volume for signal collection.

## Abstract

An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purpose the H35DEMO, a large area HV-CMOS demonstrator chip, was designed by KIT, IFAE and University of Liverpool, and produced in AMS 350 nm CMOS technology. It consists of four pixel matrices and additional test structures. Two of the matrices include amplifiers and discriminator stages and are thus designed to be operated as monolithic detectors. In these devices the signal is mainly produced by charge drift in a small depleted volume obtained by applying a bias voltage of the order of 100 V. Moreover, to enhance the radiation hardness of the chip, this technology allows to enclose the electronics in the same deep N-WELLs which are also used as collecting electrodes. In this contribution the characterisation of H35DEMO chips and results of the very first beam test measurements of the monolithic CMOS matrices with high energetic pions at CERN SPS will be presented.

## Full text

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## Figures

14 figures with captions in the complete paper: https://tomesphere.com/paper/1705.05146/full.md

## References

7 references — full list in the complete paper: https://tomesphere.com/paper/1705.05146/full.md

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Source: https://tomesphere.com/paper/1705.05146