Testing Microfluidic Fully Programmable Valve Arrays (FPVAs)

TL;DR

This paper introduces an ILP-based testing strategy for microfluidic Fully Programmable Valve Arrays, effectively detecting manufacturing faults with minimal test vectors, thus improving reliability of next-generation microfluidic biochips.

Contribution

It presents a novel flow path and cut-set based formulation with a hierarchical ILP approach for efficient fault detection in FPVAs.

Findings

Effective fault detection with few test vectors

Hierarchical ILP strategy improves testing efficiency

Simulation confirms high fault coverage

Abstract

Fully Programmable Valve Array (FPVA) has emerged as a new architecture for the next-generation flow-based microfluidic biochips. This 2D-array consists of regularly-arranged valves, which can be dynamically configured by users to realize microfluidic devices of different shapes and sizes as well as interconnections. Additionally, the regularity of the underlying structure renders FPVAs easier to integrate on a tiny chip. However, these arrays may suffer from various manufacturing defects such as blockage and leakage in control and flow channels. Unfortunately, no efficient method is yet known for testing such a general-purpose architecture. In this paper, we present a novel formulation using the concept of flow paths and cut-sets, and describe an ILP-based hierarchical strategy for generating compact test sets that can detect multiple faults in FPVAs. Simulation results demonstrate the efficacy of the proposed method in detecting manufacturing faults with only a small number of test vectors.

Figures

Full text

See pages 1-last of FPVA_test_DATE17.pdf