PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model

TL;DR

PieceTimer introduces a comprehensive timing analysis framework that models the interdependence of clock-to-q delays, setup, and hold times using a piecewise linear approach, leading to more accurate circuit performance verification.

Contribution

It presents a novel holistic timing analysis method that captures the interdependencies between delays, setup, and hold times with a piecewise model, improving accuracy over traditional methods.

Findings

More accurate timing analysis results.

Potential for improved circuit performance.

Better modeling of flip-flop delay dependencies.

Abstract

In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The characterized delays, setup times and hold times, are ap- plied in timing analysis independently to verify the perfor- mance of circuits. In reality, however, clock-to-q delays of flip-flops depend on both setup and hold times. Instead of being constants, these delays change with respect to different setup/hold time combinations. Consequently, the simple ab- straction of setup/hold times and constant clock-to-q delays introduces inaccuracy in timing analysis. In this paper, we propose a holistic method to consider the relation between clock-to-q delays and setup/hold time combinations with a piecewise linear model. The result is more accurate than that of traditional timing analysis, and the incorporation of the interdependency between clock-to-q delays, setup times and hold times may also improve circuit performance.

Figures

Full text

See pages 1-last of PieceTimer_ICCAD2016.pdf