EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

TL;DR

EffiTest offers a fast, cost-effective method for post-silicon delay testing by using existing tuning buffers and statistical prediction, significantly reducing testing time with minimal yield loss.

Contribution

This paper introduces EffiTest, a novel framework that combines delay alignment with statistical prediction to improve post-silicon testing efficiency.

Findings

Reduces frequency stepping iterations by over 94%.

Maintains high yield with minimal loss.

Efficiently estimates delays of non-tested paths.

Abstract

At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to balance timing bud- gets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be mea- sured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from ex- pensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Exper- imental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.

Full text

See pages 1-last of EffiTest_DAC2016.pdf