Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

TL;DR

This paper presents a novel integer-linear-programming-based method for automated CMOS RFIC layout generation, achieving high-quality device placement and microstrip routing with reduced time and improved performance.

Contribution

It introduces a new optimization approach that automates RFIC layout design, significantly reducing manual effort and layout generation time while meeting stringent microstrip routing requirements.

Findings

Layout quality surpasses manual designs in performance and area.

Layout generation time reduced from weeks to half an hour.

Fewer bends in microstrip lines improve RFIC performance.

Abstract

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.

Figures

Full text

See pages 1-last of RFPandR_DAC2016.pdf