Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability

TL;DR

This paper presents a sampling-based approach for post-silicon buffer insertion to improve chip yield under process variability, balancing buffer count and range for effective yield enhancement.

Contribution

It introduces a novel sampling-based method for optimal buffer placement that reduces buffer count while maximizing yield improvement.

Findings

Achieves up to 35% yield improvement

Uses fewer buffers with smaller ranges

Effective under process variability conditions

Abstract

At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain yield. To combat this pessimism, post-silicon clock tuning buffers can be inserted into circuits to balance timing budgets of critical paths with their neighbors. After manufacturing, these clock buffers can be configured for each chip individually so that chips with timing failures may be rescued to improve yield. In this paper, we propose a sampling-based method to determine the proper locations of these buffers. The goal of this buffer insertion is to reduce the number of buffers and their ranges, while still maintaining a good yield improvement. Experimental results demonstrate that our algorithm can achieve a significant yield improvement (up to 35%) with only a small number of buffers.

Figures

Full text

See pages 1-last of Sampling_Buffer_Insertion_DATE2016.pdf