Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements

TL;DR

This paper introduces a fast, graph-based timing analysis method for circuits with post-silicon clock tuning elements, significantly reducing computation time while accurately evaluating performance and critical gates.

Contribution

It presents a novel graph transformation algorithm for parametric minimum clock period computation, outperforming Monte Carlo simulation in speed and accuracy.

Findings

Over 10,000 times faster than Monte Carlo simulation

Accurately identifies critical gates affecting performance

Provides efficient performance evaluation for post-silicon tuning circuits

Abstract

Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so that clock skews to these flip-flops can be adjusted after man- ufacturing. Owing to the delay compensation across consecutive register stages enabled by the clock tuning elements, higher yield and enhanced robustness can be achieved. These benefits are, nonetheless, attained by increasing die area due to the inserted clock tuning elements. For balancing performance improvement and area cost, an efficient timing analysis algorithm is needed to evaluate the performance of such a circuit. So far this evaluation is only possible by Monte Carlo simulation which is very timing- consuming. In this paper, we propose an alternative method using graph transformation, which computes a parametric minimum clock period and is more than 10 4 times faster than Monte Carlo simulation while maintaining a good accuracy. This method also identifies the gates that are critical to circuit performance, so that a fast analysis-optimization flow becomes possible.

Figures

Full text

See pages 1-last of SSTA_PST_TCAD_2015_11.pdf