# On Timing Model Extraction and Hierarchical Statistical Timing Analysis

## TL;DR

This paper presents methods for extracting hierarchical timing models for different circuit types to enable faster statistical timing analysis of complex chips while preserving confidentiality and accuracy.

## Contribution

It introduces novel techniques for timing model extraction and correlation reconstruction in hierarchical designs, improving analysis speed without exposing detailed circuit information.

## Key findings

- Full-chip timing analysis is several times faster with the proposed models.
- The accuracy of statistical timing analysis is maintained.
- The methods are applicable to combinational, flip-flop-based, and latch-controlled circuits.

## Abstract

In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained.