# Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations

## TL;DR

This paper introduces an efficient statistical timing analysis method for latch-controlled circuits that reduces computational effort by combining reduced iterations and graph transformations, enabling faster yield estimation.

## Contribution

It proposes a novel combination of reduced iterations and graph transformations to significantly improve the efficiency of statistical timing analysis for latch circuits.

## Key findings

- Over 10 times faster than existing methods
- Provides parametric minimum clock period for yield calculation
- Handles nonpositive loops effectively

## Abstract

Level-sensitive latches are widely used in high- performance designs. For such circuits efficient statistical timing analysis algorithms are needed to take increasing process vari- ations into account. But existing methods solving this problem are still computationally expensive and can only provide the yield at a given clock period. In this paper we propose a method combining reduced iterations and graph transformations. The reduced iterations extract setup time constraints and identify a subgraph for the following graph transformations handling the constraints from nonpositive loops. The combined algorithms are very efficient, more than 10 times faster than other existing methods, and result in a parametric minimum clock period, which together with the hold time constraints can be used to compute the yield at any given clock period very easily.