Reconfiguring the Imaging Pipeline for Computer Vision
Mark Buckler, Suren Jayasuriya, Adrian Sampson

TL;DR
This paper proposes a reconfigurable imaging pipeline that switches between high-quality photography and low-power vision modes, significantly reducing energy consumption with minimal impact on vision accuracy.
Contribution
It introduces a configurable imaging pipeline and a sensor design that enables energy-efficient vision modes by skipping certain ISP stages.
Findings
Disabling ISP stages like demosaicing and gamma compression has minimal impact on vision accuracy.
The proposed sensor design with adjustable resolution and tunable ADCs enables 75% energy savings.
Vision mode reduces energy consumption while maintaining acceptable task performance.
Abstract
Advancements in deep learning have ignited an explosion of research on efficient hardware for embedded computer vision. Hardware vision acceleration, however, does not address the cost of capturing and processing the image data that feeds these algorithms. We examine the role of the image signal processing (ISP) pipeline in computer vision to identify opportunities to reduce computation and save energy. The key insight is that imaging pipelines should be designed to be configurable: to switch between a traditional photography mode and a low-power vision mode that produces lower-quality image data suitable only for computer vision. We use eight computer vision algorithms and a reversible pipeline simulation tool to study the imaging system's impact on vision performance. For both CNN-based and classical vision algorithms, we observe that only two ISP stages, demosaicing and gamma…
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Taxonomy
TopicsCCD and CMOS Imaging Sensors · Image Processing Techniques and Applications · Advanced Neural Network Applications
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