# Towards Reduced Instruction Sets for Synchronization

**Authors:** Rati Gelashvili, Idit Keidar, Alexander Spiegelman, Roger Wattenhofer

arXiv: 1705.02808 · 2017-05-09

## TL;DR

This paper demonstrates that a lock-free, linearizable log data-structure can be implemented using only weaker synchronization instructions like decrement and fetch-and-increment, challenging the necessity of compare-and-swap.

## Contribution

The authors design and implement a concurrent log data-structure using only weaker atomic instructions, reducing the synchronization instruction set needed for concurrent algorithms.

## Key findings

- Supports wait-free reads and lock-free writes.
- Achieves performance comparable to compare-and-swap-based solutions.
- Uses only atomic read, xor, decrement, fetch-and-increment instructions.

## Abstract

Contrary to common belief, a recent work by Ellen, Gelashvili, Shavit, and Zhu has shown that computability does not require multicore architectures to support "strong" synchronization instructions like compare-and-swap, as opposed to combinations of "weaker" instructions like decrement and multiply. However, this is the status quo, and in turn, most efficient concurrent data-structures heavily rely on compare-and-swap (e.g. for swinging pointers and in general, conflict resolution).   We show that this need not be the case, by designing and implementing a concurrent linearizable Log data-structure (also known as a History object), supporting two operations: append(item), which appends the item to the log, and get-log(), which returns the appended items so far, in order. Readers are wait-free and writers are lock-free, and this data-structure can be used in a lock-free universal construction to implement any concurrent object with a given sequential specification. Our implementation uses atomic read, xor, decrement, and fetch-and-increment instructions supported on X86 architectures, and provides similar performance to a compare-and-swap-based solution on today's hardware. This raises a fundamental question about minimal set of synchronization instructions that the architectures have to support.

## Full text

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## Figures

1 figure with captions in the complete paper: https://tomesphere.com/paper/1705.02808/full.md

## References

8 references — full list in the complete paper: https://tomesphere.com/paper/1705.02808/full.md

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Source: https://tomesphere.com/paper/1705.02808