A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development

TL;DR

This paper introduces a scalable, low-overhead FPGA overlay architecture that significantly reduces resource usage and compilation time for finite-state machines, enhancing rapid development and flexibility.

Contribution

The authors present a novel overlay architecture using memory decomposition that improves scalability, flexibility, and compilation speed for FPGA-based finite-state machine implementation.

Findings

15-29% fewer lookup tables for individual FSMs

77-99% reduction in lookup tables for multiple FSMs

Compilation time reduced to tenths of a second

Abstract

Productivity issues such as lengthy compilation and limited code reuse have restricted usage of field-programmable gate arrays (FPGAs), despite significant technical advantages. Recent work into overlays -- virtual coarse-grained architectures implemented atop FPGAs -- has aimed to address these concerns through abstraction, but have mostly focused on pipelined applications with minimal control requirements. Although research has introduced overlays for finite-state machines, those architectures suffer from limited scalability and flexibility, which we address with a new overlay architecture using memory decomposition on transitional logic. Although our overlay provides modest average improvements of 15% to 29% fewer lookup tables for individual finite-state machines, for the more common usage of an overlay supporting different finite-state machines, our overlay achieves a 77% to 99% reduction in lookup tables. In addition, our overlay reduces compilation time to tenths of a second to enable rapid iterative-development methodologies.