Static Timing Model Extraction for Combinational Circuits

TL;DR

This paper presents a deterministic method for extracting compact and accurate static timing models for combinational circuits, significantly reducing model size while maintaining precision, thereby improving hierarchical static timing analysis efficiency.

Contribution

A novel timing model extraction technique that removes redundant information, achieving substantial size reduction without sacrificing accuracy in static timing analysis.

Findings

84% reduction in edges of timing models

85% reduction in vertices of timing models

Outperforms existing methods in size reduction

Abstract

For large circuits, static timing analysis (STA) needs to be performed in a hierarchical manner to achieve higher performance in arrival time propagation. In hierarchical STA, efficient and accurate timing models of sub-modules need to be created. We propose a timing model extraction method that significantly reduces the size of timing models without losing any accuracy by removing redundant timing information. Circuit components which do not contribute to the delay of any input to output pair are removed. The proposed method is deterministic. Compared to the original models, the numbers of edges and vertices of the resulting timing models are reduced by 84% and 85% on average, respectively, which are significantly more than the results achieved by other methods.

Full text

See pages 1-last of Timing_Model_PATMOS2008.pdf