Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

TL;DR

This paper reports on the development of a advanced superconducting fabrication process featuring nine layers, 250 nm features, and self-shunted Josephson junctions, aiming to improve superconducting circuit integration.

Contribution

It introduces a novel fabrication process with multiple superconducting layers, self-shunted Josephson junctions, and 250 nm feature size, enhancing circuit complexity and performance.

Findings

Mutual inductance data for Nb stripline and microstrip inductors at 250 nm to 1 μm

Linewidth and resistance uniformity measurements

Demonstration of a 250-nm fully planarized process with multiple layers

Abstract

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 {\mu}m made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.