# Steep-slope Hysteresis-free Negative Capacitance MoS2 Transistors

**Authors:** Mengwei Si, Chun-Jung Su, Chunsheng Jiang, Nathan J. Conrad, Hong, Zhou, Kerry D. Maize, Gang Qiu, Chien-Ting Wu, Ali Shakouri, Muhammad A. Alam, and Peide D. Ye

arXiv: 1704.06865 · 2018-01-31

## TL;DR

This paper demonstrates a novel MoS2 negative capacitance FET with a ferroelectric layer that achieves steep subthreshold slope and hysteresis-free operation, surpassing the thermionic limit for low-power electronics.

## Contribution

It introduces the first MoS2 steep-slope transistor with a ferroelectric HZO layer, combining 2D semiconductors with negative capacitance to improve device performance.

## Key findings

- Achieved sub-60 mV/dec subthreshold slope.
- Observed negative differential resistance at room temperature.
- Demonstrated high on-current and hysteresis-free operation.

## Abstract

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {\mu}A/{\mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied.

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Source: https://tomesphere.com/paper/1704.06865