# A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems

## TL;DR

This paper introduces a dynamic multi-level cell STTRAM cache design that adapts to workload demands, improving performance and energy efficiency while balancing cache lifetime in multi-core systems.

## Contribution

It proposes a novel adaptive cache architecture leveraging MLC STTRAM's asymmetry and SLC mode deactivation to optimize performance and energy use.

## Key findings

- 43% reduction in conflict misses
- 27% decrease in memory access latency
- 12% improvement in system performance

## Abstract

In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set capacity and associativity to use efficiently the full potential of MLC STTRAM. We exploit the asymmetric nature of the MLC storage scheme to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other is write-friendly. Furthermore, we propose to opportunistically deactivate ways in underutilized sets to convert MLC to Single-Level Cell (SLC) mode, which features overall better performance and lifetime. Our ultimate goal is to build a cache architecture that combines the capacity advantages of MLC and performance/energy advantages of SLC. Our experiments show an improvement of 43% in total numbers of conflict misses, 27% in memory access latency, 12% in system performance, and 26% in LLC access energy, with a slight degradation in cache lifetime (about 7%) compared to an SLC cache.